登录
首页 » VHDL » verilog prescaler for the realization of the odd

verilog prescaler for the realization of the odd

于 2022-08-08 发布 文件大小:578.00 B
0 109
下载积分: 2 下载次数: 1

代码说明:

verilog实现的奇数分频器 针对任何规模的奇数分频-verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • smartWasher
    QUARTER编程环境实现的智能洗衣机系统,通过DE0板子进行模拟,组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)
    2020-11-06 13:19:49下载
    积分:1
  • EPM570
    非常好的EPM570(CPLD)学习程序源码,适合初学者,能让其快速入门(Very good EPM570 (CPLD) learning program source code, suitable for beginners, allowing its Quick Start)
    2013-09-11 10:18:59下载
    积分:1
  • autosell-verilog
    实现简单自动售货机的基本功能。投币找零功能,并用Led数码管显示,输出结果用Led显示。(Basic functions simple vending machines. Coin change for function and use Led digital tube display, the output display Led.)
    2014-07-26 21:50:07下载
    积分:1
  • VHDL-development
    VHDL入门级好教材《VHDL开发精解与实例剖析》(VHDL development solution with fine examples of analysis)
    2015-03-11 10:57:53下载
    积分:1
  • 利用VHDL语言设计一个分频器,输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024...
    利用VHDL语言设计一个分频器,输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024
    2022-06-02 16:58:00下载
    积分:1
  • Altera公司的DE2平台的VGA接口的应用程序,从上到下KEY0
    ALTERA的DE2平台VGA接口应用,由KEY0-KEY3控制上下左右,使屏幕上光标移动,由Verilog描述。-ALTERA the DE2 platform VGA interface applications, from top to bottom KEY0-KEY3 about control, so that the screen cursor by the Verilog description.
    2022-09-28 16:00:04下载
    积分:1
  • 数码管显示
    在FPGA EGO1的口袋平台上实现数码管滚动显示学号的功能(Rolling on the digital tube to display the school number)
    2021-04-17 10:08:52下载
    积分:1
  • 3Verilog语言要素
    说明:  Verilog学习文档,介绍基本知识点,语言要素(for learning Verilog)
    2020-03-24 10:01:15下载
    积分:1
  • dft
    verilog语言实在点变换DFT源代码,可以配合软核或者其他CPU进行综合FFT变换,也可以单独使用生成module!(verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!)
    2009-05-09 14:29:47下载
    积分:1
  • LMS
    least mean square algo implemented on verilog
    2017-11-01 05:01:56下载
    积分:1
  • 696518资源总数
  • 106174会员总数
  • 31今日下载