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VHDL
EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。
(EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.)
- 2011-06-22 21:23:30下载
- 积分：1
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Chapter7-Sample
SAA7113 ＦＰＧＡ开发实例，非常经典(The SAA7113 FPGA development examples, very classic)
- 2012-12-06 17:00:25下载
- 积分：1
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VerilogFreq-div
Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法(Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide)
- 2013-01-21 21:45:08下载
- 积分：1
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fpga 基于FPGA的mif文件创建与使用
fpga 基于FPGA的mif文件创建与使用-fpga FPGA-based mif file creation and use of
- 2022-02-06 23:23:12下载
- 积分：1
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32位二进制除法器2
- 2023-01-06 11:10:03下载
- 积分：1
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FPGA数字AGC(帮同学做的毕业设计)
FPGA数字AGC(帮同学做的毕业设计)-FPGA digital AGC (help students to do the graduation project)
- 2022-03-17 18:29:50下载
- 积分：1
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elc_clock
verilog实践 elc_clock 电子时钟设计(Verilog design practice elc_clock electronic clock)
- 2008-12-10 16:06:48下载
- 积分：1
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saw
verilog编写，巧妙的通过计数方式完成了三角波的波形，可直接对da输出。(verilog written, cleverly accomplished by counting the triangular waveform can be output directly to da.)
- 2015-04-16 21:06:15下载
- 积分：1
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multiply_8_VHDL
由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方
法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)
- 2014-04-11 16:58:04下载
- 积分：1
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LM
用于生成adams或recurdyn所需的路面不平度，用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)
- 2013-10-15 17:38:48下载
- 积分：1
