-
rs232
用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)
- 2015-08-21 20:26:16下载
- 积分：1
-
vending-machine
用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)
- 2013-11-30 20:25:34下载
- 积分：1
-
vhdl写的ds18b20程序，相互交流
vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange
- 2022-03-19 16:58:50下载
- 积分：1
-
SYSTEMVIEWQPSK
使用 System view 编程 QPSK(use System Programming view QPSK)
- 2021-01-04 21:38:54下载
- 积分：1
-
M_SSB_100
由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)
- 2007-07-25 14:59:29下载
- 积分：1
-
vhdl语言描述分频器，实现2、4、8、16……分频，经过实践
vhdl语言描述分频器，实现2、4、8、16……分频，经过实践-description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of
- 2022-10-30 11:40:03下载
- 积分：1
-
the-verilog-code-of-can-usb-i2c
CAN总线，I2C，USB等的FPGA实现源码(CAN bus, I2C, USB, etc. FPGA implementation source)
- 2012-12-15 01:25:33下载
- 积分：1
-
RS2
该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)
- 2012-09-09 13:04:41下载
- 积分：1
-
Digital Design and Modeling with VHDL and Synthesis
Digital Design and Modeling with VHDL and Synthesis
- 2023-06-22 18:35:14下载
- 积分：1
-
verilog hdl coding DDR sdram control for fpga
verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
- 2022-03-23 21:20:26下载
- 积分：1
