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RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助...
RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助-RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder
- 2022-08-20 11:45:06下载
- 积分：1
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Matlab
说明： Matlab源程序，包括插值计算、积分微分等。(Matlab source code, including the interpolation calculations, differential and so on.)
- 2010-04-08 19:26:28下载
- 积分：1
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DAC0832
DAC0832的Verilog代码，适用于与ADC0809同时学习，效果明显！(DAC0832 Verilog code, applicable at the same time with ADC0809 learning, the effect is obvious!)
- 2012-10-17 11:04:32下载
- 积分：1
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telephone-cost-metering
该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分：1
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DW8051_ALL
包中包括,
DW8051完整的Verilog HDL代码
两本手册:
DesignWare Library DW8051 MacroCell, Datasheet
DesignWare DW8051 MacroCell Databook
三篇51论文:
基于IP 核的PSTN 短消息终端SoC 软硬件协同设计
Embedded TCP/ IP Chip Based on DW8051 Core
以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)
- 2021-05-07 09:28:36下载
- 积分：1
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LPC总线从设备的verilog设计,包含状态机和中断功能。
LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
- 2022-01-28 17:10:12下载
- 积分：1
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lowpass
低通滤波器（由matlab和simulink两种方法实现）源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)
- 2013-03-13 18:36:40下载
- 积分：1
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fpga_sdram_inst
nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)
- 2013-08-24 22:26:31下载
- 积分：1
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VHDL的重要PPT资料,对初学者非常有益处
VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners
- 2023-05-02 18:55:09下载
- 积分：1
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用verilog写的很好的cpu core
用verilog写的很好的cpu core-using Verilog write a good cpu core
- 2023-06-03 16:40:03下载
- 积分：1
