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Divider can be very good VHDL divider realize the function of great help for beg...
除法器,可以很好的实现VHDL除法器的功能对于初学者有很大帮助.
-Divider can be very good VHDL divider realize the function of great help for beginners.
- 2022-04-21 12:12:32下载
- 积分：1
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Datasheets
关于ALTERA DE2板上的文档资料，包括应用实例，用户文档和板上常用器件的技术文档(datasheets of ALTERA DE2)
- 2010-03-10 10:14:08下载
- 积分：1
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Program to implement convolution of two signals.
Program to implement convolution of two signals.
- 2023-04-30 22:25:04下载
- 积分：1
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Avgt_jesd204b_ad9250_ed
基于avgt开发板的jesd204b源代码，需要安装Quartus软件(Avgt development board based on the jesd204b source code)
- 2020-11-26 14:29:32下载
- 积分：1
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dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过.
dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, water lamp demonstration. code test.
- 2023-08-11 06:35:04下载
- 积分：1
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led1
点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)
- 2020-06-16 07:00:01下载
- 积分：1
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SPI_Master
此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用
(This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)
- 2021-02-25 09:19:38下载
- 积分：1
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main
完整的GMSK调制及维特比译码，程序中包括了高斯滤波器的设计，调制相位的计算，并采用了维特比译码算法解调出原始码元，最后计算了其误码率。(Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate.)
- 2020-11-03 16:19:54下载
- 积分：1
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pedometer
本文设计了基于加速度传感器的计步器，并通过仿真以及实际调试得到了相应的结果的记录。本实验首先通过加速度传感器检测目标物体的运动，产生脉冲，将脉冲放大后经过施密特触发器整型为方波，并给出了方波的调试电路图。然后编写程序，利用D触发器检测方波的上升沿，当上升沿到来时，计数，并对十位、个位分别编码，然后由使能信号交替控制数码管输出结果。本文给出了仿真以及调试的程序、结果。(This article is designed pedometer-based acceleration sensor and the corresponding results recorded by simulation and debugging. The experiments by first acceleration sensor detects the movement of the target object, generates a pulse, the pulse amplification is a square wave after the Schmitt trigger integer, and gives the the debug circuit diagram of a square wave. Then write procedures, the use of the rising edge of the detection of the square wave of the D flip-flop, when the rising edge, the count, and ten bits are encoded, and then alternately by the enable signal output of the digital control. In this paper, a simulation and debugging procedures, results.)
- 2013-03-13 08:58:22下载
- 积分：1
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verilog_rtl
关于LDPC解码的verilog程序，包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)
- 2015-10-29 15:42:03下载
- 积分：1
