以太网PHY层中的组成部分 8B10B编码器(Part of the Ethernet PHY layer in 8B10B encoder )

基于单片机的DDS数字信号发生器设计，可以产生正弦波。三角波等(Design of DDS digital signal generator based on MCU, can produce sine wave. Triangular wave)

Xilinx FPGA moving data across asynchronous clock boundaries

自己编的VHDL的波形发生器 做信号的可以-BOXING

DE0_PWM_LED_DRİ VE_Sİ MULATİ ON

几个fpga竞赛的设计例-Several Example FPGA design contest

这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。(This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact)

it is a new describng system for it field

电梯控制 记忆，上升下降停站 超载报警故障.....。-Verilog EDA dianti

VERILOG实现无分频时钟，包括测试文件，经过验证可用(VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication)