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基于Basys3的贪吃蛇小游戏
基于Basy3的贪吃蛇小游戏，实现了相关功能。(Snake Eating Game Based on Basy3)
- 2021-03-10 20:39:26下载
- 积分：1
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dds
基于DDS和SOPC的谐波信号发射器，拥有可调节的频率，阶段和谐波比例的谐波信号发射器由本文所设计。(Based on DDS and SOPC harmonic signal transmitter, with adjustable frequency, phase and harmonic proportion of harmonic signal transmitter designed by this article.)
- 2016-04-26 09:21:50下载
- 积分：1
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VGA显示程序，显示生日快乐
程序是自己编写的，程序的主要功能是实现VGA显示。显示画面为“生日快乐”，并且显示有蛋糕图形。生日快乐四个字可在屏幕上进行流动显示。
- 2022-05-30 10:25:57下载
- 积分：1
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五子棋verilog
资源描述五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog五子棋verilog
- 2022-04-08 19:23:01下载
- 积分：1
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turbo_encode
turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)
- 2014-03-29 15:09:58下载
- 积分：1
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EDanDanAssistg
蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ，经测试
(Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)
- 2012-09-10 00:33:07下载
- 积分：1
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complex_timing_by_Primetime
用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
- 2012-08-05 19:07:47下载
- 积分：1
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pipline_lms_and_rls_verilog
流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)
- 2021-05-06 20:58:37下载
- 积分：1
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ADC_Ctrl
简单的12位的AD转换实现，模数转换，实现模拟量转化为数字量，并在液晶显示屏上显示出转化结果，我自己下载到板子，运行正常.
- 2022-03-26 09:04:08下载
- 积分：1
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spi_slave
FPGA实现SPI接口的从机功能，接收和发送全双工运行，接收到的数据以八位LED灯显示(FPGA to achieve the SPI interface the machine function, receive and send full-duplex operation, the received data to eight LED lights)
- 2021-01-07 19:28:52下载
- 积分：1
