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LCD1602 verilog
LCD1602显示源码，verilog编写，已在版上测试过！可输入字符串显示！！！！！！！！
- 2022-07-13 15:52:45下载
- 积分：1
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基于优先级的调度
我做了一种基于进程的优先级的调度算法。因为调度是最重要的事情现在要执行更快的运行速度。因此我的设计中 verilog 的基础，进程的优先级调度算法。
- 2022-03-12 18:48:45下载
- 积分：1
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ug835-vivado-tcl-commands
说明： Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
- 2020-10-26 22:50:00下载
- 积分：1
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veye_mipi
说明： 1、 例程功能VEYE-290-LVDS模组视频接入演示。（显示设备必须支持1080p/30或1080p/25的帧率）
Veye模组—>MIA701开发板—>HDMI显示设备
2、 本例程硬件平台
MIA701-PCIE开发板，FPGA芯片：XC7A100TFGG484
3、 软件平台Vivado2018.1。
4、 附件含开发板原理图（底板+核心板）(1. Video access demonstration of routine function VEYE-290-LVDS module. (Display devices must support 1080p/30 or 1080p/25 frame rates) Veye Module - > MIA701 Development Board - > HDMI Display Equipment 2. The hardware platform of this routine MIA701-PCIE development board, FPGA chip: XC7A100TFG484 3. Software platform Vivado 2018.1. 4. Appendix contains schematic diagram of development board (bottom + core board))
- 2019-04-01 11:08:04下载
- 积分：1
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FM_DemodNew
FM接收机 基于FPGA的调频收音机的设计
用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真(FM receiver on FPGA FM receiver design
With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation)
- 2021-04-07 12:49:01下载
- 积分：1
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9850sin_function
ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)
- 2013-08-27 15:13:29下载
- 积分：1
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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分：1
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业界标准的Verilog语法格式
verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分：1
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OFDM_CP
ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)
- 2013-05-29 10:10:23下载
- 积分：1
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greedy_snake
基于Basys2开发板实现VGA输出，PS/2键盘接入的贪吃蛇游戏，键盘上下左右控制方向，小键盘+键控制速度，小键盘回车开始游戏，空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)
- 2021-03-27 17:09:12下载
- 积分：1
