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modbus_latest.tar
modbus的fpga实现。opencores上最新版本。使用fpga实现，可以大大提高响应速度，对其功能进行模块化。(modbus of fpga implementation. opencores the latest version. Use fpga implementation, can greatly improve the response speed, its function modularity.)
- 2020-10-22 10:37:23下载
- 积分：1
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50846288C
verilog 硬件编程实现bpsk调制(verilog hardware, programming bpsk Modulation)
- 2009-10-29 20:20:33下载
- 积分：1
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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分：1
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cnt
在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)
- 2014-11-03 19:35:21下载
- 积分：1
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seven-voting
用verilog 语言实现七人投票表决器(verilog seven voting)
- 2020-09-24 10:57:48下载
- 积分：1
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sdram_epm570_uart
基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)
- 2014-06-03 20:27:45下载
- 积分：1
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SDRAM
基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
- 2018-01-16 11:24:03下载
- 积分：1
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P2S
Parallel to Serial converter Module
- 2013-07-27 18:06:44下载
- 积分：1
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pwm_smg_display
用三个按键控制pwm输出
key0控制是选着显示/改变频率或占空比
key1控制增加
key2控制减少
数码管显示频率或占空比
频率单位默认Hz（500-20KHz）
占空比范围（0.1-0.9）(Control PWM output with three keys
Key0 controls display/change frequency or duty cycle optionally
Key1 controls the increase
Key2 controls are reduced
Digital tube display frequency or duty ratio
Frequency unit default Hz (500-20khz)
Duty cycle range (0.1-0.9))
- 2020-06-17 15:42:35下载
- 积分：1
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Mano-CPU_VHDL-Implementation
Mano s cpu for Man s instructions
- 2012-04-28 01:04:57下载
- 积分：1
