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ConvolutionWithViterbiDecoding
QPSK调制下的（5,7）卷积码的编码和维特比译码与BPSK调制下（5,7）卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)
- 2020-12-12 20:09:15下载
- 积分：1
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234
在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下
变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所
采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字
下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了
数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)
- 2021-03-16 21:29:21下载
- 积分：1
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3-8译码器实验
3-8译码器实验，用三个拨码开关控制8个LED中某一个点亮
- 2023-05-23 17:35:03下载
- 积分：1
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Random_Derandom
通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。(Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.)
- 2020-08-12 13:38:27下载
- 积分：1
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AD9117芯片配置程序
说明： 实现AD9117芯片的配置功能，这是一款DAC芯片(Realize the configuration function of ad9117 chip, which is a DAC chip)
- 2020-07-07 16:58:58下载
- 积分：1
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Quartus II
quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
- 2022-08-09 10:55:42下载
- 积分：1
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实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。...
实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.
- 2022-12-20 07:25:03下载
- 积分：1
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通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成...
通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成-Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation
- 2022-03-14 12:44:53下载
- 积分：1
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updown
VHDL Programmes -2 for dumping on FPGA
- 2014-02-12 00:22:46下载
- 积分：1
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Verilog HDL系列和转换的准备。我用电流输出类型。股份有限公司...
Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
- 2022-06-18 11:27:00下载
- 积分：1
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