登录
首页 » VHDL » FFT的VHDL代码

FFT的VHDL代码

于 2022-08-24 发布 文件大小:567.81 kB
0 141
下载积分: 2 下载次数: 1

代码说明:

FFT VHDL code

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • edk91i_mb_ref_guide
    embedded development kit 9.1 user guide
    2009-05-22 19:17:10下载
    积分:1
  • SignalTapII学习笔记
    说明:  学习fpga的工具signaltap软件使用说明书,好工具(Learn the instruction manual of signaltap software, a good tool)
    2020-03-29 17:59:18下载
    积分:1
  • gmsk
    产生高斯最小相移键控信号的阐述仿真,包括调制解调、信道模型等。(Simulation program to realize GMSK transmission system)
    2020-11-14 19:49:42下载
    积分:1
  • 一个交通灯的vhdl语言实现 用 VC的  1.在指定的文件夹内查找某个文件      2.获取系统文件夹的路径, 要求显示windows system tem...
    一个交通灯的vhdl语言实现 用 VC的  1.在指定的文件夹内查找某个文件      2.获取系统文件夹的路径, 要求显示windows system temp 当前目录的路径 C语言  跳马问题:在5*5的棋盘上,以编号为1的点出发,按日只跳马,要求不重复地跳所有位置,求出符合规则所有跳马的方案     1  6  15  10  21     14 9  20  5   16     19 2  7   22  11     8  13 24  17  4     25 18 3   12  23 -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23
    2022-02-14 11:48:06下载
    积分:1
  • 6级流水,verilog实现浮点数的加法,其中浮点数格式符合IEEE754标准...
    6级流水,verilog实现浮点数的加法,其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
    2023-09-01 12:35:04下载
    积分:1
  • 分别用分频比交错法及累加器分频法完成非整数分频器设计。...
    分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
    2022-01-25 23:28:15下载
    积分:1
  • music
    说明:  是用VHDL语言编写的乐曲演奏程序,详细的写了各个模块的子程序(VHDL language is the music playing program)
    2009-08-17 08:52:31下载
    积分:1
  • FPGAVHDL
    vhdl例程代码大全,包含流水灯,数码管,AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)
    2020-12-17 12:19:13下载
    积分:1
  • 1pps
    说明:  fpga程序,产生1pps脉冲信号,使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
    2020-06-20 17:00:01下载
    积分:1
  • DE2_115_Synthesizer
    FPGA implementation of simple Multi-tone Electronic Keyboard using DE2-115 board with a PS/2 keyboard and speaker
    2013-08-20 19:48:32下载
    积分:1
  • 696516资源总数
  • 106415会员总数
  • 3今日下载