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Multisim
multisim 程序
使用教程 详细明了清楚(multisim tutorial program uses more clearly understand)
- 2010-09-15 22:56:42下载
- 积分:1
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Electronic clock and simulation of VHDL procedures vhdl source code
电子时钟VHDL程序与仿真的vhdl源代码-Electronic clock and simulation of VHDL procedures vhdl source code
- 2022-01-28 11:10:39下载
- 积分:1
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AD9826-verilog
使用Verilog编写的ad9826的控制模块(the module of ad9826 with verilog)
- 2016-05-09 14:45:37下载
- 积分:1
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SoC验证的方法和技巧
SOC Verfication Methodology and Techniques
- 2022-06-14 22:50:41下载
- 积分:1
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spartan6_GTP
基于xilinx公司的SPARTAN6系列芯片的高速全双工串行收发器(high-speed transceiver based on spartan 6 of Xilinx PFGA)
- 2018-03-08 23:14:30下载
- 积分:1
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I2C_CSDN
verilog 编写的I2C程序,控制D/A的(I2C program written by Verilog to control D/A)
- 2020-06-18 21:20:02下载
- 积分:1
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xc3s400芯片详细的英文资料,xc3s400的FPGA开发板使用者必看
xc3s400芯片详细的英文资料,xc3s400的FPGA开发板使用者必看-chip xc3s400 detailed information in English, xc3s400 the FPGA development board users see
- 2023-09-02 13:00:04下载
- 积分:1
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CfgDDS_9910
dds ad9910配置的verilog hdl程序,模块化设计,输入待配置的数据,字长,启动信号,即可自动产生时序,完成一次配置,模块还有done握手信号,方便用户调用时,反复多次配置。(dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done handshake, user-friendly call, repeatedly configuration .)
- 2015-04-21 22:03:50下载
- 积分:1
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VGA
本科毕业设计,简易逻辑分析仪,重点在于用CPLD搭建显卡,输出VGA信号驱动显示器显示逻辑波形(A design for LA,use cpld to generate VGA signals.)
- 2014-04-28 11:22:01下载
- 积分:1
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从两个小的产生更广泛的ALU
Generating a wider ALU from two small ones
- 2022-07-18 07:53:37下载
- 积分:1