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Verilog计数器、编码器、加法器
verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)
- 2019-01-26 21:50:01下载
- 积分：1
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LCD12864
LCD12864的显示程序，使用的是verilog语言编写的显示程序，为PDF文档(LCD12864 display program, using Verilog language display program, as a PDF document)
- 2013-05-11 09:53:44下载
- 积分：1
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FPGA基于PCIE的DMA测试
利用ISE工具，完成对v6系列的FPGA上PCIE以及DMA数据测试仿真，可以通过编译产生仿真波形，也可以根据自己的开发板烧录到自己的板子上
- 2023-08-18 13:05:05下载
- 积分：1
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adder32
原理图输入法制作的32位加法器。。。。。。。。(adder32)
- 2009-12-29 19:32:52下载
- 积分：1
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Verilog
这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)
- 2011-11-06 13:18:07下载
- 积分：1
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i2sound_volume_control
通过代码控制音频编/解码硬件芯片WM8731，
通过按键控制音频输出的音量(Audio codec hardware chip WM8731 is controlled by code, and audio output volume is controlled by keys.)
- 2018-11-27 14:39:51下载
- 积分：1
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key_debounce-source-code
这是fpga按键消抖的源代码，在很多fpga按键实验中都可以用到，能够进行代码移植。(This is the source code of the FPGA buttons, in many FPGA key experiments can be used, and can carry out code.)
- 2015-10-31 10:19:03下载
- 积分：1
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A4_Uart_Top
说明： 串口！ 这是一个使用的通信程序 ， 非常好用。(serial port Serial port! This is a communication program used, very useful.)
- 2020-06-17 14:00:01下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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DCT_IDCT
H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码(H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code)
- 2011-06-11 07:08:30下载
- 积分：1
