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line_four
利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)
- 2020-12-01 14:59:27下载
- 积分：1
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isjtc
Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.
- 2017-08-14 17:01:39下载
- 积分：1
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DE0_VGA
利用FPGA设计游戏设计，真人版超级玛丽，VGA显示(Using FPGA design game design, live-action version of Super Mario, VGA display)
- 2020-11-06 13:09:55下载
- 积分：1
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mmuart
说明： 简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)
- 2020-06-23 20:00:01下载
- 积分：1
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32-bit ALU for the MIPS150 Processor using Verilog code
&MIPS150处理器的32位ALU测试台请随意编辑此测试台以添加其他功能。请注意，此测试台仅测试ALU的正确操作，不会检查是否将正确的值多路传输到ALU的输入中。
- 2022-03-11 18:43:22下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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new
说明： vivado2017.4下的串口通信的Verilog源码，一次传输8位，包括发送模块，接受模块，顶层模块(Verilog source code for serial communication under vivado 2017.4, which transmits 8 bits at a time, including sending module, receiving module and top module)
- 2020-06-22 20:20:01下载
- 积分：1
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EDA_C2262
Quartus_II_9.0破解器有明确的破解Quartus_II_9.0的步骤(Quartus_II_9. 0 cracked the clear cracked Quartus_II_9. 0 steps)
- 2011-11-07 21:31:47下载
- 积分：1
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FPGA_Based_CNN-master
这个项目是一个基于FPGA的alexnet第一卷积层实现。(This project is a FPGA based implementation of first Convolutional Layer of AlexNet.)
- 2017-08-27 11:00:48下载
- 积分：1
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LIFO堆栈实现(verilog)
包含三个文件，lifo主程序，sram代码，lifo测试程序
- 2022-01-24 17:21:25下载
- 积分：1
