-
24_Timer
使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
- 2021-04-27 21:38:44下载
- 积分：1
-
BPSK
说明： 八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。(Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.)
- 2011-02-24 13:15:15下载
- 积分：1
-
Features: Based on the VHDL language, realize high
功能：基于VHDL语言，实现对高速A/D器件TLC5510控制-Features: Based on the VHDL language, realize high-speed A/D control devices TLC5510
- 2022-11-12 08:45:02下载
- 积分：1
-
fulladd
this files in Quartus2 are fulladder
- 2016-05-17 16:38:42下载
- 积分：1
-
HDL的例子源代码3 / 5
HDL example source code 3/5
jkff_a
- 2022-07-26 15:52:59下载
- 积分：1
-
Verilog_add_div_multi_exp
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)
- 2020-12-18 09:49:10下载
- 积分：1
-
SignalTapII学习笔记
说明： 学习fpga的工具signaltap软件使用说明书，好工具(Learn the instruction manual of signaltap software, a good tool)
- 2020-03-29 17:59:18下载
- 积分：1
-
FPGA_can
实现基于FPGA的控制MCP2515发送的程序，本人编写通过测试，希望提供帮助(FPGA-based control program sent MCP2515, I write to pass the test, hoping to help)
- 2020-12-31 09:28:59下载
- 积分：1
-
Verilog 下 16位除法算法程序，高精度，固定17个时钟周期
Verilog 下 16位除法算法程序，高精度，固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles
- 2022-01-27 13:18:06下载
- 积分：1
-
使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。
使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
- 2022-12-07 20:00:03下载
- 积分：1
