登录
首页 » VHDL » Altera的CycloneIII Start Board,使用的PFGA是3C25,包括原理图和PCB,用Cadence Allegro打开...

Altera的CycloneIII Start Board,使用的PFGA是3C25,包括原理图和PCB,用Cadence Allegro打开...

于 2022-10-05 发布 文件大小:1.41 MB
0 145
下载积分: 2 下载次数: 1

代码说明:

Altera的CycloneIII Start Board,使用的PFGA是3C25,包括原理图和PCB,用Cadence Allegro打开-Altera

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • SystemVerilog_For_Design_Springer_2nd_Ed_2006
    SystemVerilog For Design (Springer-2nd_Ed-2006)
    2009-10-08 02:57:28下载
    积分:1
  • 16位元浮点数CPU,可作运算,以VHDL编写
    16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
    2022-05-17 06:20:07下载
    积分:1
  • 5.7
    设计一个简单的FIR滤波器,并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)
    2015-04-17 18:26:49下载
    积分:1
  • soft for changing Verilog code to c++ code ,c code
    将Verilog代码转换成C++代码的软件,C源代码。-soft for changing Verilog code to c++ code ,c code
    2022-01-24 14:30:24下载
    积分:1
  • sigma-delta-modulator
    实现SIGMA-DELTA Modulator的veriolog代码(sigma-delta moudulator for RFPLL )
    2020-11-11 13:39:44下载
    积分:1
  • BoneMicoren
    Bone microphnoe simulator. this is a trial to de-noise the bone microphone signals. This also utilizes om-lsa algorithm
    2012-12-12 04:47:28下载
    积分:1
  • alu
    this file is vhdl code of alu
    2016-05-29 16:35:58下载
    积分:1
  • oc_i2c_master_top_v92
    I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
    2009-10-10 10:43:18下载
    积分:1
  • 3P3_wimdow
    图像插值算法,窗口为3*3,用于图像的除去死点,以及提高清晰度或者使图像柔和(3*3 window)
    2012-02-28 15:36:02下载
    积分:1
  • 基于sopc ep2c5开发板的rs232例程
    基于sopc ep2c5开发板的rs232例程-On sopc ep2c5 development board rs232 routines
    2022-02-05 03:28:05下载
    积分:1
  • 696516资源总数
  • 106783会员总数
  • 25今日下载