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Read_SPI_ADC
This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
- 2015-10-13 14:43:13下载
- 积分:1
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7 digital display decoder design 7 Digital is pure combinational circuits, usual...
7段数码显示译码器设计7段数码是纯组合电路,通常的小规模专用IC,如74或4000系列的器件只能作十进制BCD码译码,然而数字系统中的数据处理和运算都是二进制的,所以输出表达都是十六进制的,为了满足十六进制数的译码显示,最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器,输出信号LED7S的7位分别接数码管的7个段,高位在左,低位在右。例如当LED7S输出为“1101101”时,数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1;接有高电平的段发亮,于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
- 2022-08-11 21:55:01下载
- 积分:1
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edge_detect_p
用于检测信号上升沿,输出与时钟相关的正脉冲(Detect the rising edge of the signal)
- 2012-03-27 14:49:21下载
- 积分:1
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vhdl
code for fft non synthesisable in xilinx ise
- 2013-09-30 13:16:13下载
- 积分:1
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adc7606
给FPGA程序,使之产生信号,驱动AD7606读取数据,并行模式。(give FPGA signal to read AD7606)
- 2021-03-29 21:39:10下载
- 积分:1
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异步串行接口电路及数据传输模块设计
设计要求1) 每帧数据供 10 位,其中 1位启动, 8位数据, 1位 停止。2) 波特率为: 9600 。3) 收发误码率
- 2023-09-07 19:10:03下载
- 积分:1
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四位十进制频率计的顶层控制模块,用于生成测频需要的复位及控制信号...
四位十进制频率计的顶层控制模块,用于生成测频需要的复位及控制信号-four decimal frequency of top-level control modules, used to generate the required frequency measurement and control signals reset
- 2022-07-22 04:02:23下载
- 积分:1
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扩频通信的Verilog工程
扩频通信的Verilog工程,对从事无线通信的工程人员有参考作用。(Spread spectrum communication Verilog project, engaged in wireless communications engineering staff reference.)
- 2017-06-11 10:29:12下载
- 积分:1
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cpu
cache,实现了部分简单指令,仿真模拟确认可行(Single-cycle CPU, to achieve some simple instruction, simulation confirm feasible)
- 2015-01-05 14:11:10下载
- 积分:1
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LEDtest
vhdl 实现fpga 闪灯控制 流水线闪灯 还用signalTAP进行检测,给初学者参考(vhdl fpga flash control lines to achieve flash is also used signalTAP testing, to advanced users)
- 2010-06-10 16:27:57下载
- 积分:1