登录
首页 » VHDL » 16 point radix 2

16 point radix 2

于 2022-10-05 发布 文件大小:9.26 kB
0 85
下载积分: 2 下载次数: 1

代码说明:

使用 c languageit 的 16 点基 2 fft 代码将 16 点时间域序列转换为频率域

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 收集了目前关于FPGA设计的论坛,大家如果有什么疑问,可以到这些论坛上求助。...
    收集了目前关于FPGA设计的论坛,大家如果有什么疑问,可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.
    2023-07-21 21:55:02下载
    积分:1
  • huffman
    huffman transform in vhdl language
    2013-08-26 13:17:15下载
    积分:1
  • DE2_Top
    Verilog代码,适合于初学者进行学习,是基于DE2平台的代码。(Verilog code, suitable for beginners to learn, is based on the DE2 platform code.)
    2008-03-24 16:11:58下载
    积分:1
  • qpsk_demod_use_FPGA
    根据软件无线电的思想,提出了一种新颖的数字信号处理算法,对QPSK信号的相位进行数字化处理,从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差,用数字锁相实现收发端载波的同步,在频偏较大的情况下,估算频偏的大小,自适应设置环路的带宽,实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台,并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点,符合未来通信技术发展的方向。(According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.)
    2010-12-06 10:52:36下载
    积分:1
  • E VHDL数字电路设计
    VHDL数字电路设计的电子书,很好的学习材料-VHDL digital circuit design of e-books, very good learning materials
    2023-01-18 23:30:04下载
    积分:1
  • Writing-a-VHDL-Testbench
    《编写VHDL测试概述》的英文原版讲述了如何使用VHDL写测试凳程序("Writing VHDL test overview" of the English original to write about how to use VHDL test bench program)
    2014-04-03 21:57:01下载
    积分:1
  • SD_rtl
    用verilog实现sd卡读写,亲测可用(Implementation of SD card read and write with Verilog)
    2020-12-27 21:49:02下载
    积分:1
  • QMD
    说明:  实现了QPSK的调制,使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)
    2019-05-05 15:37:58下载
    积分:1
  • VGA altera detailed description of the official routine Verilog code for a very...
    详细介绍了VGA官方例程Verilog代码,非常好很实用
    2022-08-21 17:43:09下载
    积分:1
  • VHDLdepinlvji
    基于VHDL的数字频率计的设计.pdf 基于VHDL的频率计设计 很好用的 希望要用的同志来下载 (基于VHDL的频率计设计 很好用的 希望要用的同志来下载 )
    2020-07-14 09:38:51下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载