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cic_4_dec
实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波(Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter)
- 2008-07-08 16:23:03下载
- 积分：1
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fftverilog
关于FFT实现的Verilog代码，(FFT realize on the Verilog code,)
- 2008-02-28 14:02:22下载
- 积分：1
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以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。...
以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。-VHDL language before learning to do procedures in an electronic alarm clock, you can realize hours, minutes and seconds of time and from time to time, school time, alarm clock, the whole point timekeeping function.
- 2022-05-06 21:47:35下载
- 积分：1
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S05_example_Network
vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)
- 2020-06-17 11:40:02下载
- 积分：1
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2
说明： Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes.
The representation step specifies the mapping the phenotypes onto a set of genotypes.
Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space.
Chromosome, and individual can be used for points in the genotye space.
Elements of a chromosome are called genes. A value of a gene is called an allele.
Variation Operators
The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.
- 2014-12-22 22:54:47下载
- 积分：1
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e_BIU
说明： isa MEMORY PLAN eu biu asm
- 2020-06-25 19:20:02下载
- 积分：1
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VHDL_course
VHDL实用教程，详细介绍VHDL语法、开发环境、应用实例等。。。(VHDL course)
- 2021-04-01 13:29:08下载
- 积分：1
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Marquee procedures described in VHDL, for beginners to practice
VHDL描述的跑马灯程序，用于初学者练习-Marquee procedures described in VHDL, for beginners to practice
- 2022-05-27 22:24:01下载
- 积分：1
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用VHDL编写的RS232串口的通信程序
用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program
- 2022-05-06 01:41:31下载
- 积分：1
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multi8x8
节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)
- 2006-12-07 13:22:48下载
- 积分：1
