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agc_gen2
AGC(自动增益放大) Verilog代码 设计可以参考 第二部分(AGC (automatic gain control) can refer to the Verilog code design
)
- 2015-04-14 01:17:31下载
- 积分:1
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The use of Altera' s FPGA
使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对4x4键盘的输入控制,并显示在一个8段式数码管上。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 the development board to realize 4x4 keyboard input control, and displayed in an eight-stage digital pipe.
- 2022-09-23 11:15:03下载
- 积分:1
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RISC
32 bit RISC Processor with 3 stage pipeline
- 2010-03-03 00:09:16下载
- 积分:1
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CPU
用Verilog实现的 哈佛结构的简单指令集CPU程序,由ALU、地址译码器、指令译码器等部分组成(Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.)
- 2016-05-22 10:07:29下载
- 积分:1
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vhdl
说明: 学习VHDL可以用得上,有很多实例,可以对照着自己写一些东西(VHDL can be useful to learn, there are many examples, can be done to write something)
- 2008-10-31 20:59:04下载
- 积分:1
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LMS自适应均衡器
在通信系统中的信道带来了重要的作用。通道可以涉及许多不同类型的扭曲我们的信息。尤其是无线信道的多径失真严重。而且更严重的是这种失真是随机的。为了解决这个问题,多渠道的影响需要在均衡器接收端。这种均衡器采用不同的学习算法连续识别通道。该项目是VHDL实现LMS学习算法流水线架构。所以这个实施可以工作以更高的数据速率以较少的时钟速度的要求,因此以较少的功耗
- 2022-01-29 00:11:01下载
- 积分:1
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exercise3
用verilog实现dsp与Fpga接口的同步设计,其功能包括读写操作及四个功能模块,采用两个fifo实现不同时钟域的地址与数据的转换,在quartus ii11.0环境下运行,运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分:1
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UART
字长可以简单调整,即可实现任意字长UART通讯(The word length can be simply adjusted to achieve any word length UART communication.)
- 2018-07-09 22:06:02下载
- 积分:1
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12
说明: 用FPGA进行等精度频率和相位差测量的程序,本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)
- 2010-03-03 17:42:11下载
- 积分:1
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qiangdaqi
本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)
- 2013-10-30 14:48:21下载
- 积分:1