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The design of digital self
数字平律己的设计非常实用 黄永显示早设计大方ijasd-The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd
- 2022-08-10 00:17:42下载
- 积分：1
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author: Richard Herveille
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman)
-- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr
-- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman)-- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt-
- 2022-03-20 23:45:27下载
- 积分：1
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HB1
半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)
- 2020-12-23 10:29:06下载
- 积分：1
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det
double edfe trigger d latch
- 2014-01-07 19:55:29下载
- 积分：1
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FPGA
fpga 设计全攻略，很好的fpga入门提高资料(the fpga design Raiders, good fpga the Getting Started improve data)
- 2012-12-09 19:03:23下载
- 积分：1
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直接频率合成，Quicklogic提供,部分源文件是Quicklogic 专用文件
直接频率合成，Quicklogic提供,部分源文件是Quicklogic 专用文件-direct frequency synthesis, pioneered provide some source document is dedicated ESP
- 2022-01-25 17:31:05下载
- 积分：1
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FPGA 的数字传输比
计算多少次，把小砂轮安装数字传输比率是车轮的在一个更大完全旋转旋
- 2022-03-19 23:13:15下载
- 积分：1
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vhdlsource
用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了(Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the)
- 2007-11-30 15:56:27下载
- 积分：1
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Array-multiplier
Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
- 2015-02-21 12:59:12下载
- 积分：1
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基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。...
基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。
- 2023-02-09 02:35:04下载
- 积分：1
