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FPGA_Book_cd
《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，本书内容还是非常丰富的，涉及无线通信领域各个方面。不过对于一些比较新的技术，其FPGA实现部分过于简略，难以在工程中实用化。(" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of this book is still very rich, involved in all aspects of the field of wireless communications. But for some relatively new technology, some of its FPGA implementation is too brief, it is difficult in practical engineering.)
- 2009-10-26 14:50:33下载
- 积分：1
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CAN--for-FPGA
FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错(FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA)
- 2011-04-19 18:51:12下载
- 积分：1
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ISE为开发环境，Verilog语言编写程序
以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分：1
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chap12
《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)
- 2007-07-01 16:33:31下载
- 积分：1
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DongHo
design a clock using KIT DE1
- 2014-09-19 04:46:23下载
- 积分：1
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多thershod电源
静态功耗减少使用多 thershld< 跨度 style="font-size:12.0pt;line-height:115%;font-family:"color:#222222;background:white ；"> 多阈值 CMOStransistors 是非常手术滴备用泄漏功率 duringwhen IC 为较长时间内不活动。最近，功率 gatingscheme 提出了维护多个关闭电源模式和减小电极电源甚至短的不活跃时期。但是，这种系统能进行从高灵敏度对工艺参数变化。我们建议新浇注逻辑开关，是容错过程和 reducepower 在任何数字电路。预计的提案需要很少的金额项目努力和妥协降低功耗较大和较低的面积开销比早些时候的方法。此外，它可以团结生存系统 toproposition 额外的静态功耗减少方面受益。考试广泛娱乐的成果证明成功的拟议的设计
- 2023-03-16 10:55:03下载
- 积分：1
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使用从Digilent Spartan3E板VGA接口。LabVIEW VI
VGA interface using Spartan3E board from DIGILENT.Labview .vi
- 2023-02-15 00:10:04下载
- 积分：1
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AVS motion compensation circuit of VLSI Design and Implementation of a standard...
AVS运动补偿电路的VLSI设计与实现
提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流
水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优
利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.
- 2022-01-21 20:19:47下载
- 积分：1
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pci_fpga
对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)
- 2013-10-12 11:39:45下载
- 积分：1
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一个小程序,弹跳消除电路,可消除按健的毛刺干扰
一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference
- 2022-05-14 03:36:36下载
- 积分：1
