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PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛,本例用VHDL描述了一个锁相环作为参考,源码已经调试过...
PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛,本例用VHDL描述了一个锁相环作为参考,源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上;顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
- 2022-02-01 22:27:36下载
- 积分:1
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lunwen
一个完整的基于FPGA的IIR低通滤波器的设计方案,是一个研究生论文(master and doctor dissertation)
- 2013-05-12 20:01:14下载
- 积分:1
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这是一个HDB3编码器,可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列...
这是一个HDB3编码器,可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence
- 2022-12-15 13:45:03下载
- 积分:1
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在altera DE2 的开发板上采集图像,到lcd显示的原程序 。
在altera DE2 的开发板上采集图像,到lcd显示的原程序 。-In altera DE2 development board collecting images, lcd display to the original procedure.
- 2022-06-20 13:14:46下载
- 积分:1
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JIAOTONGDENG
用VERILOG实现 交通灯控制,且运行正确,希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)
- 2014-01-05 20:38:03下载
- 积分:1
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hwref
spartan 3 hardware reference document xilinx
- 2009-05-22 19:10:33下载
- 积分:1
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《CPLDFPGA verilog DA0832调控
verilog da0832 cpldfpga control-verilog da0832 cpldfpga control
- 2022-12-07 05:55:03下载
- 积分:1
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介绍了FPGA设计的十大准则,对初学者很有用,对于工作多年的同志,也会有整理总结的好处...
介绍了FPGA设计的十大准则,对初学者很有用,对于工作多年的同志,也会有整理总结的好处-Describes the FPGA design of the top ten criteria are useful for beginners, for many years comrades, there will be finishing the benefits of the summary
- 2022-05-09 01:58:50下载
- 积分:1
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VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)
VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)
- 2022-01-25 18:25:54下载
- 积分:1
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ds180_7Series_Overview
对赛灵思7系列的三种型号的FPGA进行了综述(xilinx 7 productin overview)
- 2012-06-13 15:04:23下载
- 积分:1