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Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
Qutuas II v7.1的key_gen 对sp1无效
这就是个v7.1 sp1的key_gen
-Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
- 2023-07-28 18:25:02下载
- 积分:1
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CPLD LATTICE1032测试模式代码
CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code
- 2022-04-01 10:27:47下载
- 积分:1
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I write the digital phase
本人写的数字锁相环,有模拟数据,学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book
- 2023-04-23 05:25:03下载
- 积分:1
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JTAG
边界扫描技术相关资料,含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分:1
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LMS算法FPGA仿真
自适应滤波器算法LMS ,的FPGA实现,采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)
- 2020-06-24 01:00:02下载
- 积分:1
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shift_registers
Universal Shift Register
- 2009-06-12 17:29:13下载
- 积分:1
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key_test
fpga的按键程序,实现按键和led的对应点亮。(The key program of FPGA realizes the corresponding lighting between keys and led.)
- 2018-04-13 00:00:28下载
- 积分:1
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regress-900055
The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.
- 2013-12-27 00:29:58下载
- 积分:1
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logic lock 的vhdl源码,altera平台适用。
logic lock 的vhdl源码,altera平台适用。-logic lock the VHDL source code, altera platform.
- 2023-01-30 09:50:04下载
- 积分:1
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多人抢答器 源代码 实用 课程设计 用用VHDL语言
多人抢答器 源代码 实用 课程设计 用用VHDL语言-The source code for more than Responder practical courses designed for use with the VHDL language
- 2022-04-21 18:03:26下载
- 积分:1