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fpga clock design, the information is better, for your reference, non

于 2022-10-20 发布文件大小:2.70 kB

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fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

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cordic_dds
采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

2015-08-18 16:15:17下载

积分：1
8051MCU in the FPGA to achieve the source code, using VHDL language
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2022-02-22 06:28:53下载

积分：1
11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合...
11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated

2022-10-31 17:45:02下载

积分：1
wide_cbf
宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)

2013-03-19 09:40:45下载

积分：1
CH4CH2CH1VHDL 数字电路参考书所有程序9
CH4CH2CH1VHDL 数字电路参考书所有程序9-CH4CH2CH1VHDL digital circuit reference all proceedings 9

2022-11-24 11:15:04下载

积分：1
adder16b
说明：潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)

2009-07-23 17:02:22下载

积分：1
FPGA-powe-analysis-tool-EPE
FPGA功耗分析工具EPE用于分析FPGA系统的功耗(FPGA power analysis tools EPE is used to analyze the power consumption of the FPGA system)

2012-11-19 17:08:00下载

积分：1
ethernet_loopback
通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)

2017-11-20 10:21:38下载

积分：1
HB1
半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

2020-12-23 10:29:06下载

积分：1
LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现
LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language

2022-12-16 00:40:03下载

积分：1

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fpga clock design, the information is better, for your reference, non

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