-
ass1_3_safe
The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last
- 2011-03-05 01:17:22下载
- 积分：1
-
FSK
频移键控FSK的Verilog实现，带测试文件，并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)
- 2020-09-03 11:28:07下载
- 积分：1
-
fpga_ofdm
这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用，大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)
- 2007-06-13 00:02:43下载
- 积分：1
-
改进的DCT算法设计，veriloghdl实现
改进的DCT算法设计，veriloghdl实现-Improved DCT algorithm design, veriloghdl realize
- 2022-03-07 20:38:18下载
- 积分：1
-
VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1
VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months
- 2022-05-22 16:09:28下载
- 积分：1
-
basys3_timing
基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL(Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL)
- 2016-03-06 11:08:18下载
- 积分：1
-
BMD_PCIE
自己根据xapp1052修改的源代码，已经编译成功，并应用在开发板上。(According xapp1052 own modified source code has been successfully compiled and used in the development board.)
- 2015-10-19 08:10:20下载
- 积分：1
-
eth_send
清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。(Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.)
- 2010-09-26 14:43:28下载
- 积分：1
-
详细介绍了VHDL的28个程序。从简单到复杂。介绍详细
详细介绍了VHDL的28个程序。从简单到复杂。介绍详细-Details of the 28 procedures VHDL. From simple to complex. Detailed introduction
- 2022-07-24 10:14:53下载
- 积分：1
-
xapp1026
XILINX中LWIP协议例子应用指南，有实际例子(Examples of applications in LWIP agreement XILINX Guide, a practical example)
- 2020-10-13 22:07:32下载
- 积分：1
