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FSK
FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。(FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.)
- 2020-09-03 11:38:07下载
- 积分：1
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附件 介绍了如何 使用compxlib命令编译Xilinx的ModelSim仿真库，创建这个仿真库对ISE调用modelsim是必不可少的一步,该法完全自动化，...
附件 介绍了如何 使用compxlib命令编译Xilinx的ModelSim仿真库，创建这个仿真库对ISE调用modelsim是必不可少的一步,该法完全自动化，免去繁杂的手动操作，是创建这个仿真库最简洁的方法之一-Annex compxlib introduce how to use Xilinx
- 2022-03-15 17:10:01下载
- 积分：1
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vhdl um teste com muita coisa interessante ae pra ver
vhdl um teste com muita coisa interessante ae pra ver
- 2023-07-05 20:40:02下载
- 积分：1
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verilog program for 8
verilog program for 8-bit multiplier
- 2023-07-15 11:05:03下载
- 积分：1
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MP3-coder
In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder.
Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them
includes all the VHDL source codes of the component.)
- 2013-08-06 15:40:24下载
- 积分：1
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uart
一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)
- 2013-07-25 11:43:34下载
- 积分：1
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I121-v1.10
Implementation of Serial Infrared decoder for low-speed IrDA communications.
- 2013-06-14 05:38:14下载
- 积分：1
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lisa-vhdl2va
通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)
- 2013-12-12 11:17:18下载
- 积分：1
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dpll
数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法(Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods)
- 2017-04-04 23:13:28下载
- 积分：1
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32位ALU
这个我弄了好久，伤心了。不过，自己喜欢，终于把他给做了出来，过程是相当的复杂，不信。你们可以下下来看看，有不懂得可以咨询我
- 2022-03-04 00:04:32下载
- 积分：1
