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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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tb_modular
Matlab to hdl code for Least_square testbench
- 2020-06-17 12:20:02下载
- 积分：1
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FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。
FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。-FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.
- 2023-05-07 13:55:03下载
- 积分：1
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VGAzifuxianshi
用VERILOG编写的VGA字符显示，可以在电脑屏幕上显示字符,已通过测试(Prepared with the VERILOG VGA character display, can display characters on a computer screen, has been tested)
- 2011-01-01 14:50:47下载
- 积分：1
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simple_cpu
初学cpu结构的很好的verilog代码的示例，适合初学者(novice cpu structure of the good verilog code examples for beginners)
- 2007-03-03 01:05:16下载
- 积分：1
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4
通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic
communication )
- 2013-09-29 09:51:55下载
- 积分：1
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SPI经典ip核
可以直接用于工程的开发和利用
SPI经典ip核
可以直接用于工程的开发和利用-err
- 2023-02-04 19:10:03下载
- 积分：1
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一个用FPGA语言设计数字秒表的程序，有相关的源程序和说明
一个用FPGA语言设计数字秒表的程序，有相关的源程序和说明-FPGA design using a digital stopwatch language of the procedures and instructions related to the source
- 2022-02-02 02:15:47下载
- 积分：1
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sch_tbf
Token Bucket Filter queue.
- 2013-05-06 11:34:24下载
- 积分：1
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CICFilter
文章运用分级抽取和多相滤波的方法改进传统CIC滤波器的结构,降低了系统工作频率,运用幅度改进函数(ACF)和外加级联余弦预滤波器的技术改进了滤波器频率响应,提出了一种高效的算法结构,改善了通带损耗,增大了阻带衰减,对CIC滤波器的实际应用和深入研究有着现实意义。
(Article the use of hierarchical multi-phase extraction and filtering methods to improve the structure of the traditional CIC filter, reducing the system operating frequency, the use of margin to improve the function (ACF) and the cosine cascade plus pre-filter technology to improve the filter frequency response, the an efficient algorithm to improve the pass-band loss, increases the stopband attenuation of the CIC filter in practical applications and in-depth study has practical significance.)
- 2020-08-14 11:08:27下载
- 积分：1
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