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i2c_master
verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
- 2017-06-15 16:30:14下载
- 积分：1
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数字相位
PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
- 2023-05-28 08:00:03下载
- 积分：1
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这个程序可以帮助转换成BCD码excess3代码，完美…
this the program which can help to convert bcd code to excess3 code,the perfect circuitary has been given in this document which will lead you to understand it more properly.Reference is taken from morris mano book of digital electronics.This program can work on quatrus without any trouble.this is also used to make a final year -this is the program which can help to convert bcd code to excess3 code,the perfect circuitary has been given in this document which will lead you to understand it more properly.Reference is taken from morris mano book of digital electronics.This program can work on quatrus without any trouble.this is also used to make a final year
- 2022-03-16 21:25:25下载
- 积分：1
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基于FPGA的DDS程序代码
基于FPGA的DDS程序代码，实现的功能强大可以输正弦波，三角波，方波等波形，并且频率可以调节。实现对应的功能强大。(FPGA-based DDS program code can achieve powerful output sine wave, triangle wave, square wave waveform and frequency can be adjusted. Implement corresponding powerful.)
- 2015-09-15 23:09:00下载
- 积分：1
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用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL...
用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
- 2022-05-14 13:34:13下载
- 积分：1
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数字频率计VHDL程序
数字频率计VHDL程序
--文件名：plj.vhd。
--功能：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的
--高4位进行动态显示。小数点表示是千位，即KHz。-Digital Cymometer VHDL procedures- File name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for the high dynamic display. Decimal point that is 1000, or KHz.
- 2022-05-21 22:31:32下载
- 积分：1
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VHDLFIFO
用Verilog 写一个8x16 的FIFO，完成先入先出的功能，并且在FIFO读空时输出EMPTY
有效信号，读指针RP 不再移动；FIFO 写满时输出FULL 有效信号，并且即使WR 有效也
不再向存储单元中写入数据(写指针WP 不再移动)。
(NO)
- 2020-09-20 20:17:51下载
- 积分：1
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fpga数码管显示
让你EJ疼没人开门吗维护和输入热火男的竟然也可以看看一份心疼你身边女人很多好的主人你让他愤怒和难题太难太难太难输入你的人难道她和他人的烦恼的童年听到她赫然发红包少年人反而能认识的男人的法人俄方的人体内
- 2023-01-03 09:40:17下载
- 积分：1
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imply logic
说明： 由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
- 2019-04-24 15:42:24下载
- 积分：1
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Xilinx公司Accel DSP项目
xilinx accel dsp实例项目工程-xilinx accel dsp project
- 2023-03-09 20:10:02下载
- 积分：1
