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Altera_Audio
针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1
Boards and provides an interface for audio input and output.)
- 2015-04-01 22:21:49下载
- 积分：1
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Verilog1
这个程序为通信中的16QAM调制程序，可用于无线或有线通信系统的调制仿真之用。(The 16QAM modulation communication this program can be used for wireless or wired communication system modulation simulation purposes.)
- 2013-05-16 17:30:08下载
- 积分：1
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verilog2000更新部分，请对照前一个标准。加入了一些新的支持
verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support
- 2022-02-04 06:03:56下载
- 积分：1
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SOPC_PCI
基于FPGA的pci总线接口设计。。。。。。。。。。。。。(FPGA-based PCI bus interface design)
- 2012-03-28 13:55:33下载
- 积分：1
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SimpleVOut-master
说明： SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
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Hamming_decoder-1
this program does something im not sure what but all i want is to get into the damn site thank you
- 2010-09-09 16:46:51下载
- 积分：1
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这篇文章主要是概要的阐述了如何使用
这篇文章主要是概要的阐述了如何使用-quartusⅡ+Modelsim+synplify pro，来设计FPGA系统。-This is a summary of the main article on how to use the-quartus Ⅱ+ Modelsim+ synplify pro, to design FPGA systems.
- 2022-01-26 08:00:21下载
- 积分：1
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rs232
异步串行传输的verilog hdl 功能文件以及测试文件(The verilog hdl source and the testbench of asynchronous serial transmission )
- 2009-12-27 16:02:38下载
- 积分：1
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lesson1
eda的入门学习课件，老师不错，内容页挺好的(eda learning files)
- 2012-12-14 22:39:31下载
- 积分：1
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TOFED_TB_1
A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of
output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a
circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition
diagram, a state table and a schematic for your circuit. Design an alternate implementation
using just three flip flops and draw a state transition diagram, state table and a schematic
for your circuit. If your designs are extended to implement an n bit twisted ring counter,
how many flip flops are required using each of the two approaches. In what situations
would you prefer the first method? In what situations would you prefer the second?
- 2014-11-08 06:58:55下载
- 积分：1
