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pll
用FPGA实现数字锁相环,开发环境为ISE(Using FPGA digital phase-locked loop, development environment for ISE)
- 2021-03-19 18:29:19下载
- 积分:1
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VHDL的重要PPT资料,对初学者非常有益处
VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners
- 2022-05-18 19:20:34下载
- 积分:1
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VHDL开发的计数器。源程序不复杂,应该都能看懂。最重要的注意:是时序问题
VHDL开发的计数器。源程序不复杂,应该都能看懂。最重要的注意:是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue
- 2022-05-14 00:07:18下载
- 积分:1
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VHDL开发环境,电梯控制系统,实现电梯的上下传送控制。
VHDL开发环境,电梯控制系统,实现电梯的上下传送控制。-VHDL development environment, elevator control system, transmission control up and down elevators.
- 2022-03-15 14:58:09下载
- 积分:1
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ANC_LMS
verilog描述的基于LMS的自适应噪声消除器ANC算法。用于数字音频处理。(The verilog Description LMS-based adaptive noise canceller ANC algorithm. For digital audio processing.)
- 2012-10-29 21:43:33下载
- 积分:1
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beep_interface
这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)
- 2013-05-05 21:07:18下载
- 积分:1
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01_基于ZYNQ的FPGA基础入门
说明: VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)
- 2020-06-17 12:00:01下载
- 积分:1
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基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例....
基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例.-NIOS based on the CF card applications (including the software and hardware), ALTERA the IP library provides only the bottom of the first document describes the hardware registers. This is a HAL-based IP core of the software, hardware design and the corresponding sample.
- 2022-04-25 01:03:08下载
- 积分:1
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DDR SDRAM information, interested to see friends down under
DDR SDRAM的资料,有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under
- 2022-07-22 04:07:30下载
- 积分:1
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New-Folder
to learn bout development of vhdl code
- 2014-03-15 16:21:38下载
- 积分:1