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用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。...
用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分：1
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and they simply based on the mouse xinlinx ideally VHDL application procedures,...
基于fpga和xinlinx ise的鼠标应用vhdl程序，希望对你有所帮助！-and they simply based on the mouse xinlinx ideally VHDL application procedures, and I hope to help you!
- 2022-02-18 14:46:28下载
- 积分：1
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DTMB
能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分：1
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ise
xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)
- 2007-09-20 14:30:52下载
- 积分：1
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小波变换去噪vhdl
基于小波变换去噪，采用了vhdl编写，已经在和matlab上对比过，结果准确，而且大量的节约了时间，欢迎下载，可以在quartusii中查看RTL电路，可以在modesim中仿真出结果
- 2022-02-20 11:22:37下载
- 积分：1
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ahb_slave_latest.tar
AHB 总线slave verilog实现(Implementation of AHB bus)
- 2020-06-30 13:40:02下载
- 积分：1
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18 x 18 华莱士树乘法器
经过测试的 VHDL 代码为 18 x 18 位华莱士树乘法器
- 2022-01-30 15:01:08下载
- 积分：1
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在USB contreoller CRC5块
crc5 bolck in usb contreoller
- 2022-03-06 23:01:25下载
- 积分：1
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DW_apb_wdt
verilog实现watch dog，可直接用于芯片开发中。(erilog realization watchdog, can be directly used for chip development.)
- 2020-12-25 16:09:06下载
- 积分：1
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srfft_test
基于分裂基的蝶型FFT，用C实现，经过测试，没有错误，可以直接拿去使用。(Based on the division of FFT butterfly type, use C implementation, tested, no error, can directly use.
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- 2016-05-05 22:35:40下载
- 积分：1
