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Exercise4
AES TSAPI Retrieve Event in Non-blocking Mode
- 2019-05-07 20:04:58下载
- 积分：1
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gff_int_mul
application of a galois field multiplication and normal multiplication
- 2008-05-28 16:23:11下载
- 积分：1
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traffic
说明： 模拟交通灯
verilog CPLD
EPM1270
源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)
- 2008-10-30 23:12:20下载
- 积分：1
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Altium Partner SN-1000010 r10
说明： Browser modularization processing, browser modularization combing, browser modularization expansion
- 2020-06-24 04:20:01下载
- 积分：1
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基于Actel A3P030 FPGA液晶显示器使用jdl12864串行接口，时钟可调
基于Actel A3P030 FPGA，液晶采用JDL12864串行接口，时钟48MHz-Based on Actel A3P030 FPGA, LCD using JDL12864 serial interface, clock 48MHz
- 2022-07-05 03:00:11下载
- 积分：1
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lmf
在ISE下，FPGA产生线性调频信号，并且产生信号的参数可调(In ISE, the FPGA generates a linear frequency modulation signal, and the parameters of the signal are adjustable.)
- 2018-03-29 15:31:15下载
- 积分：1
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Uses Verilog the HDL design, obtains the realization basis on
the palm space int...
采用Verilog HDL设计,在掌宇智能开发板上得到实现
根据抢答器的原理，整个电路可划分为三部分：采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on
the palm space intelligence development board to snatch the answering
principle, the entire electric circuit may divide is three parts: The
sampling electric circuit, the gate control the electric circuit and
the decoding circuit
- 2022-03-16 23:36:15下载
- 积分：1
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SystemOfTaxiFeeBasedOnVerilogHDL
摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。
关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)
- 2007-09-11 10:52:52下载
- 积分：1
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mp3_player
Altera board
Mp3 project
- 2011-12-27 15:04:02下载
- 积分：1
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13.2_MotionDetec
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)
- 2020-10-23 20:57:22下载
- 积分：1
