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ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户
ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户-Chinese ISE7.1i the xilinx tutorial for FPGA/CPLD users
- 2022-02-25 00:06:16下载
- 积分：1
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auk_sdsdi
说明： 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能(for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on)
- 2020-11-11 12:39:44下载
- 积分：1
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在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。...
在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.
- 2022-02-25 18:59:33下载
- 积分：1
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EP2C5
基于FPGA/EP2c5的开发板详细例程，内容丰富，简单易懂(Development board based on more routine FPGA/EP2c5, content rich, easy to understand)
- 2020-12-06 22:59:23下载
- 积分：1
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vga_ctl_640x480
VGA 640x480 driver in verilog
- 2010-08-16 02:48:43下载
- 积分：1
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设计含异步清零和同步时钟使能的加法计数器
设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter
- 2023-03-27 21:05:03下载
- 积分：1
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log10(x)
Fixed-point base-2 logarithm (DW_log2)
// Computes the base-2 logarithm of a fixed point value in the
// range [1,2).
- 2014-09-11 19:58:10下载
- 积分：1
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Avgt_jesd204b_ad9250_ed
基于avgt开发板的jesd204b源代码，需要安装Quartus软件(Avgt development board based on the jesd204b source code)
- 2020-11-26 14:29:32下载
- 积分：1
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DA_AD
基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)
- 2017-11-07 22:03:30下载
- 积分：1
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fullbridge_double_frequency
建立了单相的PWM整流器电路闭环控制的仿真模型。版本R2007(The simulation model of the closed-loop control of single-phase PWM rectifier circuit. Version R2007)
- 2021-02-02 09:10:00下载
- 积分：1
