-
AHB_UVC_and_AHB_IC_Verificat
ahb uvc is an on chip communication protocol for high speed integration and low power utilities performance protocols widely used in all vip applications
- 2020-10-21 12:07:24下载
- 积分:1
-
VHDL描述的简易图像缩小模块,将PAL制720×576的图片缩小为512×410,采用最近临域法,13.5MHz时钟下可实时处理PAL视频。...
VHDL描述的简易图像缩小模块,将PAL制720×576的图片缩小为512×410,采用最近临域法,13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
- 2022-06-11 23:09:14下载
- 积分:1
-
数字计时器,使用VHDL语言编写,使用数码管显示,精确到ms
数字计时器,使用VHDL语言编写,使用数码管显示,精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms
- 2022-05-20 00:23:22下载
- 积分:1
-
数字频率计数字频率计
数字频率计
数字频率计-Digital frequency meter digital frequency meter
- 2022-01-24 16:05:05下载
- 积分:1
-
电子手表
在硬件上实现,可以实现一般电子表的功能。比如说计时,显示日期,秒表等功能。还可以显示星期数,可以正常的区分闰年等。并且仿真文件也在其中,反正了其时序变化情况。比较详细。必要出有注释。
- 2022-07-08 11:11:12下载
- 积分:1
-
generate-coordinates
使用VHDL编写语言,巧妙的利用计数器和循环输出一个坐标系,由于VHDL出现负数比较麻烦,全部由正数代替,输出一个原点在中心,半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)
- 2013-08-28 11:03:46下载
- 积分:1
-
《阿东+手把手教你学FPGA》完美公开版
一本很好的教程,适合初学者,里面有详细的教程,很值得一看!!(A good tutorial, suitable for beginners, there are detailed tutorials, it is worth a visit!!)
- 2018-06-20 19:41:52下载
- 积分:1
-
VLSI implementation of high speed and high resolution FFT algorithm based on Rad...
VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application
- 2022-05-07 09:52:02下载
- 积分:1
-
从两个小的产生更广泛的ALU
Generating a wider ALU from two small ones
- 2022-07-18 07:53:37下载
- 积分:1
-
homework32
说明: 这是32位移位寄存器,是用verilog编写的,能够实现从1到31位的左或右的移位(This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right)
- 2009-07-27 15:54:00下载
- 积分:1