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ahb_master_latest.tar
AHB master总线verilog实现(Implementation of AHB master bus Verilog)
- 2020-07-01 22:20:02下载
- 积分：1
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counter (2)
This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.
- 2017-07-18 19:24:12下载
- 积分：1
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liuy
一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)
- 2010-08-25 12:26:25下载
- 积分：1
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应用硬件描述语言产生随机数，在模糊控制仿真中应用的较多...
应用硬件描述语言产生随机数，在模糊控制仿真中应用的较多-By VHDL generating random Numbers, in the application of the fuzzy control simulation
- 2022-06-15 20:13:25下载
- 积分：1
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LCD1602_B
说明： Verilog实现液晶1602显示,学习使用(Verilog LCD1602)
- 2009-08-09 10:57:02下载
- 积分：1
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JIAOTONGDENG
用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)
- 2014-01-05 20:38:03下载
- 积分：1
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用数码管显示时间的数字电子钟verilog编写
用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time
- 2022-06-22 05:51:35下载
- 积分：1
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PS2 source VHDL, and can be connected directly to the computer. So the mouse, ke...
PS2的源代码VHDL语言实现，可以和计算机直接连接．做鼠标键盘接口．-PS2 source VHDL, and can be connected directly to the computer. So the mouse, keyboard interface.
- 2022-11-10 10:10:04下载
- 积分：1
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nios2_led_one
使用nios2点亮一个led灯，使用软件quartus13.0，开发板de2-115(nios2 led quartus13.0 de2-115)
- 2013-12-11 14:32:16下载
- 积分：1
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Simulate
FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。(FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.)
- 2021-04-14 21:08:55下载
- 积分：1
