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用VHDL和约翰逊状态编码状态的有限状态机
An FSM using VHDL and Johnson state encoding for states
- 2022-04-27 12:30:31下载
- 积分：1
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source
说明： I2C MASTER DESIGNED by Verilog
- 2020-06-18 23:40:02下载
- 积分：1
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src
说明： 假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分：1
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procedures in the report, with QuartusII operations, the attention to word from...
程序在报告中，要 用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the
- 2022-03-22 23:49:36下载
- 积分：1
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VHDL数字频率计（1）频率测量范围： 10 ～ 9999Hz 。
（2）输入电压幅度 >300mV 。
（3）输入信号波形：任意周期信号。...
VHDL数字频率计（1）频率测量范围： 10 ～ 9999Hz 。
（2）输入电压幅度 >300mV 。
（3）输入信号波形：任意周期信号。
（4）显示位数： 4 位。
（5）电源： 220V 、 50Hz
-vhdl
- 2022-07-20 20:49:22下载
- 积分：1
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采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件...
采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件-AD using high-speed storage oscilloscope design, based on EP1C3 board GWADDA board storage oscilloscope, which has the documentation
- 2022-03-22 11:22:04下载
- 积分：1
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Radar-on-FPGA
主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。(Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given)
- 2012-08-11 17:51:55下载
- 积分：1
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module_dem
用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现(Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation)
- 2009-10-14 14:47:30下载
- 积分：1
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CPU流水线设计报告
说明： CPU课程设计要求以FPGA开发平台为例，分析 CPU 设计的流程与仿真。
本次开发使用的硬件描述语言是 Verilog 语言，使用的指令系统是一个以 MIPS 指令集为子集的指令系统，共 22 条指令，所用的设计仿真软件Modelsim。(CPU curriculum design requires FPGA development platform as an example to analyze the process and Simulation of CPU design.
The hardware description language used in this development is Verilog language, and the instruction system used is an instruction system with MIPS instruction set as a subset, with 22 instructions in total. The design simulation software Modelsim is used.)
- 2020-12-24 12:09:05下载
- 积分：1
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ps2接口的工程实现，顶层为原理图，便于理解
ps2接口的工程实现，顶层为原理图，便于理解-ps2 interface engineering implementation, the top-level schematic diagram for easy understanding of
- 2022-07-10 06:48:35下载
- 积分：1
