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The use of long
利用电话远程系统，通过密码验证来实现对家庭电器的智能控制。-The use of long-distance telephone system, via a password to verify the implementation of the intelligent control of household electrical appliances.
- 2022-01-31 17:55:43下载
- 积分：1
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一种学习用的小程序，主要用与VHDL仿真的全加器的一段代码！大家可以下载进行修改于仿写...
一种学习用的小程序，主要用与VHDL仿真的全加器的一段代码！大家可以下载进行修改于仿写-A learning to use a small program, mainly used with the VHDL simulation of a full-adder code! You can download the modified Yu Fang Xie
- 2022-01-25 21:36:29下载
- 积分：1
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基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！
基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
- 2022-03-13 03:44:13下载
- 积分：1
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The-NIOSII-detailed-tutorial
黑金动力原创nios ii教程，介绍了硬件、软件开发流程，提供了led、中断、串口、rtc、spi、iic、定时器等十多个实验的详细介绍(Alinx original nios ii tutorial, this paper introduces the hardware and software development process, and provides led, interrupt, a serial port, the RTC, spi, iic, timer and so on more than a dozen experiments in detail)
- 2020-12-08 15:09:21下载
- 积分：1
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apb2ahb
verilog code for apb to ahb convert
- 2021-01-05 03:38:55下载
- 积分：1
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ALU_74181_me
学习ALU的设计方法。
2、用HDL语言采用行为描述的方法完成74181的逻辑设计 。(Learn the design method of ALU.
2, use HDL language to use behavioral description method to complete 74181 logical design.)
- 2020-11-11 16:19:44下载
- 积分：1
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第七次课--视频图像DCT处理及水印嵌入_2
说明： 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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CD1_MT9V034_RAW_TRANS
基于FPGA的UDP网络图像传输实验，FPGA完成了MT9V034的RAW图像采集缓存，NIOS完成了图像的UDP封包，DM9000芯片完成了MAC和PHY的功能。(Based on the UDP FPGA network image transmission experiment, FPGA completed the RAW MT9V034 image acquisition cache, NIOS completed the image of the UDP packets, DM9000 chip MAC and PHY completed the function.)
- 2016-07-13 10:11:46下载
- 积分：1
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verilog时钟分频器~ 50hmz波特率9600bps，使用~
verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
- 2022-06-03 13:21:28下载
- 积分：1
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ahdl--sine-wave-code-with-rom-look-up-table_imp
hi this is an verilog codes
- 2011-11-11 14:30:21下载
- 积分：1
