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test_uart
基于fpga的uart串口通信协议，64位数据(Uart communication protocol based on fpga, 64-bit data)
- 2017-08-09 17:35:47下载
- 积分：1
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VHDL的您的信息的一个游戏程序的源代码，我希望那些在…
一个游戏程序vhdl源码，供大家参考，希望有兴趣的人下载-VHDL source code of a game program for your information, I hope those who are interested in downloading
- 2022-03-19 17:54:49下载
- 积分：1
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full adder in vhdl of 4 bits
full adder in vhdl of 4 bits
- 2022-02-01 04:44:39下载
- 积分：1
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N-bits-by-M-bits
这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)
- 2013-10-05 19:44:52下载
- 积分：1
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M-ary-QAM-in
研究信道噪声对M-ary QAM的影响，适合数字通讯从业者(Effect of channel noise on M-ary QAM in)
- 2015-07-15 09:45:41下载
- 积分：1
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Quartus flv configuration and commissioning of the
QUARTUS 的配置及调试
flv的
-Quartus flv configuration and commissioning of the
- 2023-08-05 13:40:04下载
- 积分：1
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SAP
SAP-1硬件描述语言（使用Verilog语言）
- 2023-06-14 11:45:03下载
- 积分：1
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costas
载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
)
- 2021-03-05 13:09:31下载
- 积分：1
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dma_ahb
挂靠在AMBA2.0的AHB总线上的DMA装置，用于直接发起数据传输。(Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.)
- 2021-03-29 21:49:10下载
- 积分：1
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at7_ex04
通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)
- 2018-04-09 18:41:52下载
- 积分：1
