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Arty-Z7-20-hdmi-out-master
Arty Z7 20 HDMI output
- 2021-04-24 15:18:47下载
- 积分：1
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TCON
用verilog编程的TCON模块（时序控制器）的程序(Verilog programming module with TCON (timing controller) program)
- 2013-06-26 10:50:59下载
- 积分：1
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Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
- 2022-04-02 05:52:39下载
- 积分：1
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adder_array
adder_array的设计。加法器阵列设计，顶层模块，四步流水，21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)
- 2013-04-17 00:19:05下载
- 积分：1
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ddr3control
8位突发长度，一次64bit数据读写，MIG核(DDR3 controll implimention)
- 2021-05-07 13:58:36下载
- 积分：1
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arbiter_ip
Arbiter code for simulation purpose
- 2013-07-13 17:45:11下载
- 积分：1
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电子闹钟：基于fpga的电子闹钟设计，采用模块化方式
电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach
- 2022-02-06 03:24:59下载
- 积分：1
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is done in the laboratory in the loss of 60 counts, and LED show.
是我们在在实验室做的摸60计数，并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.
- 2022-03-21 19:17:50下载
- 积分：1
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一个简易的数字频率计，可以对一个输入的信号频率进行测量并显示输出，适合VHDL的初学者...
一个简易的数字频率计，可以对一个输入的信号频率进行测量并显示输出，适合VHDL的初学者-A simple digital frequency meter, you can enter the signal of a frequency measurement and display output, suitable for beginners VHDL
- 2022-06-20 21:46:49下载
- 积分：1
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DE2 will connect to the LCD layout for Terasic off technology companies attached...
DE2将连接到LCD布局上，为Terasic off技术公司附上系统代码
- 2023-02-16 06:25:03下载
- 积分：1
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