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USB的vhdl代码，具有很强的指导意义，对FPGA进行usb控制很有帮助！...
USB的vhdl代码，具有很强的指导意义，对FPGA进行usb控制很有帮助！-USB vhdl code, which is of great guiding significance. the FPGA control usb helpful!
- 2022-03-13 05:49:02下载
- 积分：1
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05_fifo_test
说明： FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分：1
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交通灯电路，南北方向和东西方向分别按绿灯、黄灯、左拐灯、黄灯、红灯的顺序两灭，数码管显示相应的灯亮的时间的倒计时。已通过编译和仿真。...
交通灯电路，南北方向和东西方向分别按绿灯、黄灯、左拐灯、黄灯、红灯的顺序两灭，数码管显示相应的灯亮的时间的倒计时。已通过编译和仿真。-Traffic light circuit, north-south direction and east-west direction respectively green, yellow light, left light, yellow light, red light destroy the order of two, a digital LED display lights the corresponding period of the countdown. Has passed the compilation and simulation.
- 2023-02-22 23:25:03下载
- 积分：1
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coubter_key
ISE环境下Verilog编程实现机械按键去抖(ISE Verilog programming environment under mechanical debounces)
- 2015-12-13 12:52:42下载
- 积分：1
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VHDL.Programming
这是这本书的第四个版本，现在这个版本不仅提供了VHDL语言的覆盖面，但设计方法的信息，以及。此版本将指导读者通过创建一个VHDL设计的过程中，模拟设计，综合设计，放置和布线设计，使用的重要模拟验证的最终结果，新的技术，称为全速调试，提供了极其快速设计验证。在这个版本的设计，例如已被更新(This is the fourth version of the book and this version now not only provides VHDL language coverage but design methodology information as well. This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called At-Speed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect.)
- 2012-04-08 19:36:36下载
- 积分：1
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uart
通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)
- 2018-11-28 09:19:29下载
- 积分：1
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本项目是基于SR和D触发器的使用vhdl.this是100正确的内容。
this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2022-06-27 01:31:46下载
- 积分：1
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FPGA1(introduce)
FPGA三国论战，入门介绍和高端见解！对于FPGA初学者很有用。(Three FPGA controversy, and high-end introduction to ideas! For FPGA useful for beginners.)
- 2014-03-22 16:19:51下载
- 积分：1
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gobang
一个用verilog实现的五子棋程序，用在fpga上，连接显示器，可选择与电脑对战或是双人对战，按wsad控制方向，回车控制落子，程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)
- 2015-03-30 13:13:35下载
- 积分：1
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liyuanlnx_dynamic_led
FPGA数码管显示秒表实验
三种方法实现：
方法一： 对秒计数，得到（秒显示）0~9，
对（秒显示）计数，得到（分秒显示）0~5，
对（分秒显示）计数，得到（分钟显示）0~5，
注意进位时机
方法二： 对秒计数，得到（秒显示）0~9
对秒计数，得到（分秒显示）0~5
对秒计数，得到（分钟显示）0~5
方法三：
只对秒计数，分别取模
%60得到分钟显示 ************************
余数%10得到分秒显示 （据说）取模运算占资源！！！！（也能接受？好像...）
再剩下的余数为秒显示 ************************(Experiment of Digital Tube Display Stopwatch Based on FPGA
Three ways to achieve)
- 2020-06-22 04:40:02下载
- 积分：1
