-
Verilog_SimpleCalculator-master
这是一个计算器的Verilog代码，可实现加减乘除等基础功能(calcultor for you to do some reserches.)
- 2017-12-24 10:24:59下载
- 积分：1
-
classdiagramnew
class diagram diagram for AIRS
- 2015-06-10 22:44:10下载
- 积分：1
-
zhentongbu
ＦＰＧＡ在通信上的运用：基于VHDL的帧同步程序(Application of FPGA in communication: Based on VHDL frame synchronization procedures
)
- 2012-11-28 09:10:05下载
- 积分：1
-
dianti
6层电梯设计，采用vhdl编写，能够实验电梯功能(6-story elevator design, using vhdl prepared, able to lift function experiments)
- 2014-04-06 11:41:34下载
- 积分：1
-
shi01
FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency)
- 2017-10-24 16:41:14下载
- 积分：1
-
AHB2APB bridge verilog code
初学AMBA AHB/APB 转换协议，包括APB BRIDGE 源文件，仿真testbench verilog 源文件
- 2022-03-06 15:26:10下载
- 积分：1
-
Core1553BRT_EBR_EV_20
actel公司用于1553总线的1553BRT-EBR核心代码 包括文档和代码非常有用(Actel company for the 1553 bus 1553BRT-EBR core code, including documentation and code is very useful)
- 2021-05-06 18:58:37下载
- 积分：1
-
SimpleVOut-master
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
-
AD9267的FPGA参考设计
AD9267 10bit 640MSPS高速ADC的FPGA参考设计
Verilog语言实现
包含Xilinx ISE12.2工程
- 2023-01-04 17:30:03下载
- 积分：1
-
基于XILINX FPGA的OFDM通信系统基带设计
基于XILINX FPGA的OFDM通信系统基带设计 浙江大学出版社出版 ofdm verilog HDL语言(Baseband Design of OFDM communication system based on XILINX FPGA, published by Zhejiang University press)
- 2017-09-04 21:23:49下载
- 积分：1
