能够实现8位的无符号数的乘除法，模拟了笔算的过程

用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试 -Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test

Example of programming fifo in c

SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)

说明：  一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)

Quartus ii 入门基础 仅针对初学者 望各位童鞋们指导 呵呵 (Quartus ii entry basis only for beginners looking to guide their children' s shoes Oh you)

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

说明：  利用FPGA实现SDH开销中帧头A1A2的检测(FPGA implementation using SDH overhead in the frame header detection of A1A2)

用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法(Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm)

ahb to apb master and slave