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LIP6903CORE_CSC_RGB2YUV
CSC RGB2YUV Verilog source code
- 2011-02-28 20:06:13下载
- 积分：1
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7-segment
VHDL Design of BCD to 7-segment decoder
using PROM
- 2009-05-04 02:44:02下载
- 积分：1
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FCFS_PROJECT_A
FCFS (First Come First Served) with Database
- 2014-10-09 20:23:32下载
- 积分：1
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用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-02-13 17:47:49下载
- 积分：1
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This procedure to design an FPGA
本程序设计一个基于FPGA的4相步进电机定位控制系统。由步进电机方向设定电路模块、步进电机步进移动与定位控制模块和编码输出模块构成。前两个模块完成电机旋转方向设定，激磁方式设定和定位角度的换算等工作，后一个模块用于对换算后的角度量编码输出。-This procedure to design an FPGA-based 4-phase stepper motor positioning control system. Direction set by the stepper motor circuit module, stepper motor stepper movement and positioning control module and the code output modules. The first two modules complete the motor rotation direction setting, exciting way of setting the angle and positioning of the conversion work, after a module for the point of view of the volume of converted output encoding.
- 2022-05-09 09:25:30下载
- 积分：1
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Project7_5
基于fpga状态机的交通灯设计，亮灯时间自己修改，程序简单易懂。(Traffic light design based on FPGA state machine, light time self-modifying, the program is simple and easy to understand.)
- 2020-06-18 04:00:01下载
- 积分：1
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XAPP_585
XAPP585 serdes_1_to_7 and serdes_7_to_1 data
- 2021-02-04 13:49:57下载
- 积分：1
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8位大小比较器
说明： 8位大小比较器的VHDL源代码，Magnitude Comparator
VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)
- 2005-10-28 22:35:12下载
- 积分：1
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一种使用modelsimse6.3简单的复用方案
A program for a simple multiplexer using modelsimSE6.3
- 2022-08-20 11:51:53下载
- 积分：1
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Xilinx FPGA using leftover multipliers and block RAM
Xilinx FPGA using leftover multipliers and block RAM
- 2022-03-21 00:55:39下载
- 积分：1
