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采用VHDL编写的一个简单的UART
采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART
- 2022-03-05 06:29:41下载
- 积分：1
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16bit-multiplier
实现verilog16位乘法器，verilog新手(achieve 16-bit multiplier)
- 2021-04-01 21:09:08下载
- 积分：1
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ofdm_modulation
OFDM modulation source code written in Matlab
- 2009-06-01 17:52:44下载
- 积分：1
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基于DDS的DA正弦波输出
Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until
- 2022-01-26 04:06:16下载
- 积分：1
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GAL
有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)
- 2013-07-09 22:50:01下载
- 积分：1
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ADAPTIVEFILTER
采用vhdl代码描述自适应滤波器，具有很好的可参考性，和实用性(Vhdl code to describe the use of adaptive filter, can be found with a good nature and usefulness of)
- 2010-02-05 23:37:48下载
- 积分：1
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seven-voting
用verilog 语言实现七人投票表决器(verilog seven voting)
- 2020-09-24 10:57:48下载
- 积分：1
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altera 公司的15IP源码
亲自测试还不错 有DIV, CONTER
altera 公司的15IP源码
亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER
- 2022-03-13 02:56:46下载
- 积分：1
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ALTERA Cyclone1C20 Nios开发板，protel99格式
ALTERA Cyclone1C20 Nios开发板，protel99格式-ALTERA Cyclone1C20 Nios，protel99
- 2022-01-23 10:08:20下载
- 积分：1
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Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen
利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出-Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen
- 2023-04-13 10:15:04下载
- 积分：1
