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整个工程代码
说明: 掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序,熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)
- 2019-01-21 17:21:27下载
- 积分:1
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basys3_timing
基于Basys3的数字钟实例,主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL(Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL)
- 2016-03-06 11:08:18下载
- 积分:1
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Viterbi译码器的编解码器的设计
用Verilog实现
Viterbi译码器的编解码器的设计
用Verilog实现-Viterbi decoder。Verilog
- 2022-09-18 21:30:03下载
- 积分:1
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Single-CPU
说明: 简单的单周期CPU设计,实现的指令有:算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分:1
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uart_tr(3)
uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )
- 2015-06-08 21:02:17下载
- 积分:1
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key44
4x4鍵盤使用語法為VHDL,基於cyclone(4 x 4 keyboard using VHDL)
- 2010-05-20 00:10:47下载
- 积分:1
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digital-system-design
基于VHDL语言的七段显示管程序, 实现9个数字循环 并且能控制播放速度(SEVEN SEGMENT DISPLAY)
- 2011-02-14 21:02:38下载
- 积分:1
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Camera-Interface-Overview
主要讲述了数码相机MIPI接口协议说明,工作模式及信号传输原理等(Camera Interface Overview)
- 2014-01-20 22:19:32下载
- 积分:1
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Apply-of-turbo-code-in-LTE
turbo码在LTE中的实现,并在fpga中得到了实现(turbo code in LTE implementations, and have been achieved in fpga)
- 2021-01-14 20:28:46下载
- 积分:1
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曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取...
曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取出来作为同步信号,使接收端的时钟与发送设备的时钟保持一致-Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock
- 2023-06-17 15:30:03下载
- 积分:1