基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例.-NIOS based on the CF card applications (including the software and hardware), ALTERA the IP library provides only the bottom of the first document describes the hardware registers. This is a HAL-based IP core of the software, hardware design and the corresponding sample.

booth algotihm verilog design and test

关于一个串行数据输入 根据时序将数据分两路输出的程序 -on a serial data input timing will be based on output data using two procedures

verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)

用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

altera EP1C6Q240C6开发板原理图-altera EP1C6Q240C6 SCH

基于fpga和51单片机的等精度频率计，通过fpga对信号进行采集，数据传给单片机计算，再由12864进行显示，可进行频率，周期，脉宽，占空比，幅值等的测量。(Fpga and 51 microcontroller based precision frequency meter, through fpga for signal acquisition, data to the microcontroller to calculate, and then by 12864 for display, can be measured frequency, period, pulse width, duty cycle, the amplitude and the like.)

用verilog语言实现DCT编解码 附有DCT的说明(Using Verilog language realize DCT codec with a description of DCT)

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)