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RotaryEncoder
基于xilinx spartan 3E开发板，通过旋转编码器实现流水灯的左右移动闪烁变换。(Based on the Xilinx Spartan 3E development board, the left and right flicker transformation of the flow lamp is realized by the rotary encoder.)
- 2018-02-05 11:37:43下载
- 积分：1
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UART
Task4 for learning verilog
- 2019-05-28 12:31:15下载
- 积分：1
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ATAN_CORDIC
使用cordic算法，基于verilog实现的atan功能，经过仿真验证，适宜工程使用。(ATAN,implemented with cordic.)
- 2018-09-26 11:19:50下载
- 积分：1
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hilbert_m
基于FPGA的希尔伯特变化的verilog代码(Hilbert change verilog code)
- 2020-10-19 09:37:25下载
- 积分：1
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移位寄存器（右移和左移）
module shiftrne(R,L,E,w,Clock,Q);
parameter n=4;
input [n-1:0]R;
input L,E,w,Clock;
output reg [n-1:0]Q;
integer k;
always@(posedge Clock)
begin
if(L)
Q
- 2023-08-01 00:40:03下载
- 积分：1
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dr6—ise-F
用FPGA开发板的按键作为电子表的时间初值设置控制信号，数码管当前时间值输出。用按键选择分别输出：分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds.)
- 2017-10-11 21:19:55下载
- 积分：1
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PIP
基于FPGA的画中画处理PDF技术文档，采用SD卡里图片读出来做为底图，然后再图上叠加另外一个图片或者视频(Based on the FPGA picture in picture processing PDF technical documentation
)
- 2014-07-10 17:56:04下载
- 积分：1
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HwLog10
用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。(It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.)
- 2021-04-07 15:59:01下载
- 积分：1
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UDP
用FPGA中的三速以太网来实现UDP通信，功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)
- 2013-03-08 18:27:38下载
- 积分：1
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CH03_RGMII_UDP_TEST
基于RGMII的UDP网络数据通信，学习FPGA的千兆以太网通信(RGMII based UDP network data communication, learning FPGA Gigabit Ethernet communications)
- 2017-09-11 23:04:19下载
- 积分：1
