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traffic-light
Traffic light program in c presents what happens in our daily life at traffic light signals.
- 2012-11-06 06:50:15下载
- 积分:1
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sep_fram_v0.0
直接序列扩频系统的收发系统,可以进行参数配置(this is a Verilog program )
- 2016-03-01 13:22:03下载
- 积分:1
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How to Connecting Xilinx FPGAs to the Philips
How to Connecting Xilinx FPGAs to the Philips
- 2022-08-14 17:50:57下载
- 积分:1
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CACPU
basic cpu design in verilog
- 2016-01-11 23:26:01下载
- 积分:1
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STM32F407FFT
使用STM32官方提供的DSP库进行FFT,虽然在使用上有些不灵活(因为它是基4的FFT,所以FFT的点数必须是4^n),但其执行效率确实非常高效,看图1所示的FFT运算效率测试数据便可见一斑。该数据来自STM32 DSP库使用文档(. Using the official DSP library provided by STM32 for FFT is not flexible in use (because it is the FFT of base 4, so the number of FFT points must be 4 ^ n), but its execution efficiency is really very efficient, as can be seen from the test data of FFT operation efficiency shown in Figure 1. This data comes from STM32 DSP library usage document)
- 2020-06-20 19:00:02下载
- 积分:1
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xilinx 器件vhdl原程序,LCD控制
xilinx 器件vhdl原程序,LCD控制-Xilinx devices VHDL original procedure, LCD control
- 2023-03-04 21:15:04下载
- 积分:1
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王金明:《Verilog HDL 程序设计教程》程序
王金明:《Verilog HDL 程序设计教程》程序-Wang Jinming:
- 2023-04-09 20:15:03下载
- 积分:1
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AD9250 204b Verilog源码
说明: AD9250是一款双通道14位ADC,最高采样速率250 MSPS,JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
- 2021-04-14 11:01:55下载
- 积分:1
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国外的VHDL应用例子,大家可一好好参考一下!
国外的VHDL应用例子,大家可一好好参考一下!-abroad VHDL Application examples, we can make reference to a properly!
- 2022-01-25 20:56:43下载
- 积分:1
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FIFO_Buffer(verilog)
这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)
- 2021-04-22 13:38:49下载
- 积分:1