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用VHDL langhantdma
用VHDL语言实现TDMA编码,简单，明了。看标注就可以看懂-use vhdl langhanTDMA
- 2022-01-30 18:52:37下载
- 积分：1
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ise
xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)
- 2007-09-20 14:30:52下载
- 积分：1
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数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法...
数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different sub-frequency ratio, NC prescaler value can be used include parallel preset counter adder design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.
- 2023-04-20 16:25:03下载
- 积分：1
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Manchester-code-of-VHDL-program
利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)
- 2013-07-14 22:08:25下载
- 积分：1
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图书馆的IEEE
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_ARITH.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
- 2022-03-24 00:58:30下载
- 积分：1
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verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，11...
verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
- 2022-04-21 11:48:36下载
- 积分：1
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13.3_Tracing
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪(System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking)
- 2020-11-04 17:39:51下载
- 积分：1
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用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!
用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!-VHDL language with the image sensor TCD132D realize the timing-driven code, timing accurate!
- 2022-01-26 02:25:08下载
- 积分：1
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verilog
用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)
- 2021-04-25 20:48:46下载
- 积分：1
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很不容易找到的资料，基于VHDL的频率计设计 希望有用
很不容易找到的资料，基于VHDL的频率计设计 希望有用-Not easy to find information on the frequency meter based on the VHDL design seek to help
- 2022-04-21 13:02:06下载
- 积分：1
