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wallace_multiplier
华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)
- 2020-12-26 10:29:03下载
- 积分：1
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AD_100k
ADC Reference code!Clock 100kHz
- 2020-06-24 10:40:02下载
- 积分：1
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generateCAcode
gps C/A码生成
生成gps32颗卫星伪码，方便，经过测试(gps C/A code generation to generate pseudo-code satellites gps32, convenient and tested)
- 2021-05-13 04:30:02下载
- 积分：1
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HalfbandDec
基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。(Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.)
- 2012-10-25 11:18:40下载
- 积分：1
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固定的点复杂 FFT
固定的 128 点复杂 FFT
或
64/8/16 点
- 2022-02-06 02:51:48下载
- 积分：1
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Chapter10
第十章的代码。
本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示(Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate)
- 2009-11-17 13:52:32下载
- 积分：1
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VHDL--波形发生器
用FPGA产生正弦波、方波、三角波和锯齿波，可以通过按键控制输出波形及其频率，并且可以通过lcd显示输出的波形名字及频率
- 2022-02-12 06:23:05下载
- 积分：1
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sdh_pointer_deal
文件描述的是SDH 指针处理和系统同步代码 veriolg(SDH pointer processing and system synchronization code veriolg of file Description)
- 2012-09-07 16:17:40下载
- 积分：1
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VERILOG-CAR-TEST
基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)
- 2020-11-26 19:39:32下载
- 积分：1
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second7-02
在quartusII环境下采用对编解码芯片HD6408和HD6409驱动的方式实现曼彻斯特编解码(Environment in quartusII codec chip used on the HD6408 and HD6409-driven way to achieve encoding and decoding of Manchester)
- 2020-11-02 10:19:53下载
- 积分：1
