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FPGA programming serial communications, the entire source code. Including the si...
FPGA编程实现串口通信，源代码全。包括仿真程序。-FPGA programming serial communications, the entire source code. Including the simulation program.
- 2022-08-25 19:14:53下载
- 积分：1
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Input_filter
Module for filtering input digital signal
- 2015-03-05 16:53:07下载
- 积分：1
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VENDTEST
此为实现第14.7.9章所需的激励文件
该代码为门级RTL描述。(Stimulus file to verify Section 14.7.9
the functionality of
gate vs. RTL description.)
- 2011-08-11 15:07:16下载
- 积分：1
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ALU_verilog
用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件(Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document)
- 2008-08-15 11:36:51下载
- 积分：1
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8051的Verilog
8051的Verilog-Verilog OF 8051
- 2022-06-15 04:13:18下载
- 积分：1
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Xilinx 的DDR SDRAM控制器，用Verilog HDL描述
Xilinx 的DDR SDRAM控制器，用Verilog HDL描述-
A DDR SDRAM contraller sample descripte in Verilog HDL ,base on Xilinx FPGA
- 2022-08-12 17:31:12下载
- 积分：1
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keyscan
用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)
- 2013-09-13 22:59:11下载
- 积分：1
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uart
串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分：1
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iq_balance
调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
- 2021-04-23 17:48:47下载
- 积分：1
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Collected their own routines VHDL code, suitable for beginners to learn, I hope...
自己收集的VHDL例程代码，适合初学者学习用，希望能给大家带来帮助。-Collected their own routines VHDL code, suitable for beginners to learn, I hope we can help.
- 2022-07-02 04:49:52下载
- 积分：1
