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介绍列昂2微处理器
Inroduce the LEON 2 microprocessor
- 2022-09-20 12:25:02下载
- 积分：1
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SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps...
SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps
- 2023-01-21 19:35:04下载
- 积分：1
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adv7511_hdmi
FPGA与HDMI ADV7511接口源代码(FPGA HDMI Adv7511 interface)
- 2020-10-08 14:37:36下载
- 积分：1
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vhdl
vhdl
- 2022-06-20 13:51:22下载
- 积分：1
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seg7
SEG7数码管显示示例程序，适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)
- 2012-05-31 10:29:25下载
- 积分：1
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sram_saa1117verilog
图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)
- 2020-07-09 21:58:55下载
- 积分：1
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verilog digital stopwatch to achieve accurate to 10ms
verilog实现的数字跑表 精确到10ms-verilog digital stopwatch to achieve accurate to 10ms
- 2022-04-18 11:51:54下载
- 积分：1
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表决器，简单实现了表决功能，无显示功能
表决器，简单实现了表决功能，无显示功能 -vote
- 2022-05-17 19:43:31下载
- 积分：1
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chuankou
本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
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Signal
基于FPGA的DDS相位累加器，连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)
- 2018-05-10 15:19:05下载
- 积分：1
