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ddr_for_controller_and_phy
说明： 这是本人曾经参与的一个DDR controller接口项目，主要是FPGA rtl实现，仅供参考。(This is a DDR controller interface project that I once participated in, mainly implemented by FPGA RTL, for reference only.)
- 2020-12-21 20:59:08下载
- 积分：1
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Slave-FIFO
详细讲解Slave FIFO模式下的初始化设置和相对应寄存器说明(Explain in detail the initial setup Slave FIFO mode and the corresponding register description)
- 2014-03-18 17:33:23下载
- 积分：1
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DE2 development company for the altera board SD_Card_Audio examples
用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples
- 2022-12-25 12:55:03下载
- 积分：1
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performance-of-pcie
本白皮书探讨了在PCI Express的因素
技术可能会影响性能。它还
提供指导如何估算
的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)
- 2013-10-29 10:52:43下载
- 积分：1
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xapp1026
XILINX中LWIP协议例子应用指南，有实际例子(Examples of applications in LWIP agreement XILINX Guide, a practical example)
- 2020-10-13 22:07:32下载
- 积分：1
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time_frequency_analysis
一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)
- 2013-12-04 10:13:24下载
- 积分：1
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A signal can be stretched any one CLk the VHDL source code examples. See documen...
一个可以把信号拉长任意个CLk的VHDL源码例子。详见说明文档-A signal can be stretched any one CLk the VHDL source code examples. See documentation
- 2022-03-24 02:54:32下载
- 积分：1
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4ASKmod2
讲述4ASK的原理并附有matlab调制解调的源码。。。。。。。。。。
注：原来上传的4ASKmod.zip不要下(The principle tells 4ASK together with modulation and demodulation matlab source. . . . . . . . . . Note: The original upload 4ASKmod.zip not down)
- 2013-07-10 00:01:10下载
- 积分：1
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turbo_encode
turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)
- 2014-03-29 15:09:58下载
- 积分：1
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mdio
用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件(Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file)
- 2020-09-16 14:37:55下载
- 积分：1
