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m_xulie
在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)
- 2013-09-26 11:30:47下载
- 积分：1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分：1
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EDA应用中ROM具体定义实例，供大家学习和写程序参考之用
EDA应用中ROM具体定义实例，供大家学习和写程序参考之用-EDA applications, examples of the specific definition of ROM, for everyone to learn and write programs for reference
- 2022-07-07 21:49:00下载
- 积分：1
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gtx
ip core of the transceiver gtx
- 2019-04-02 00:10:03下载
- 积分：1
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cmp
VHDL code comparator
- 2012-06-26 18:50:52下载
- 积分：1
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zongbian4
基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)
- 2021-03-04 09:59:32下载
- 积分：1
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E VHDL数字电路设计
VHDL数字电路设计的电子书，很好的学习材料-VHDL digital circuit design of e-books, very good learning materials
- 2023-01-18 23:30:04下载
- 积分：1
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modelsim_ug
Mentor Graphics ModelSim User s Guide Software v6.3g
- 2010-04-18 13:30:25下载
- 积分：1
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exp_rom
通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)
- 2020-06-23 04:40:02下载
- 积分：1
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user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller I...
user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.
- 2022-07-06 22:09:23下载
- 积分：1
