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vjtag
说明： quartus vitual jtag代码使用接口，通过该接口模板方便使用者通过jtag在线读取FPGA的数据。(The quartus virtual JTAG code uses an interface, through which users can read FPGA data online.)
- 2020-05-06 09:42:50下载
- 积分：1
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ENDAT2.2-Code
海德汉绝对式编码器代码，VHDL语言编写(Heidenhain absolute encoder code, VHDL language)
- 2021-04-26 11:18:45下载
- 积分：1
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检测上升沿的verilog程序，有验证程序，可用synplify验证
检测上升沿的verilog程序，有验证程序，可用synplify验证-Detection of rising edge of the Verilog procedures, there is the verification process can be used to verify Synplify
- 2022-01-31 05:33:02下载
- 积分：1
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ecc算法源码
该源码表述了ecc算法如何用vhdl实现RSA（Ron Rivest，Adi Shamir，Len Adleman三位天才的名字）一样，ECC（Elliptic Curves Cryptography，椭圆曲线密码编码学）也属于公开密钥算
- 2022-03-07 00:08:00下载
- 积分：1
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sound_ranging
改VHDL代码可以实现超声波测距的功能，其精确度达到US级，可以用七段数码管显示其数值(sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging )
- 2014-06-13 20:42:03下载
- 积分：1
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processor
processor design istruction load pipeline ,hazard
- 2010-04-02 03:52:08下载
- 积分：1
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VHDL写的PWM发生器，仿真通过，波形基本完美，可以用于直流电机的控制...
VHDL写的PWM发生器，仿真通过，波形基本完美，可以用于直流电机的控制-PWM generator written in VHDL, simulation is passed, the basic waveform perfect, can be used for DC motor control
- 2022-09-19 14:15:03下载
- 积分：1
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verilog实现基于i2s协议接口 i2s_interface
verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)
- 2017-11-05 17:26:39下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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一个可用的很不错的DDS 频率合成程序，用VHDL语言编写
一个可用的很不错的DDS 频率合成程序，用VHDL语言编写-Available is a good DDS frequency synthesis procedures, using VHDL language
- 2022-11-29 23:55:03下载
- 积分：1
