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a
用verilog实现除法器,调用了ip核,不仅有源代码,还有测试程序的时序编写(verilog ise divider)
- 2013-07-21 15:03:31下载
- 积分:1
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rams
说明: combinatorial modules
- 2019-04-13 19:41:21下载
- 积分:1
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OFDM_Verilog实现
使用Verilog语法编写OFDM系统,可借鉴学习,包括发射和接收两部分,发射部分有时钟,映射,交织,加CP、长短训练符号等模块,接收部分有频偏估计,解交织,解映射,维特比译码等模块
- 2023-06-03 16:50:04下载
- 积分:1
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jjiaotongdeng
实现fpga上交通灯的设计,可以在开发板上实现红绿灯(Design of traffic lights on FPGA)
- 2018-08-28 16:42:27下载
- 积分:1
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VHDLFIR
1 由matlab计算FIR数字滤波器的滤波系数;
2 用VHDL语言设计逻辑电路,再通过QUARTUS II 软件,将各个模块的电路封装成期间,在顶层设计中通过连线,完成整个系统。
(matlab
VHDL
QUARTUS )
- 2016-05-15 12:49:30下载
- 积分:1
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FPGA
韩福柱老师FPGA实验源码,用vhdl语言在xilinx FPGA上实现,包括ad采集,温度传感器读取,秒表,跑马灯和按键次数统计4个实验(Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and keystrokes 4 experimental statistics)
- 2017-01-06 15:54:53下载
- 积分:1
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digital_lock_vga_display
Altera DE1平台的数字密码锁设计,可以驱动VGA显示(Altera DE1 platform digital password lock design, can drive VGA display)
- 2017-10-31 10:41:38下载
- 积分:1
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atom.2007.12.tar
Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C
- 2008-05-12 10:13:23下载
- 积分:1
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AMI1
本代码是用VERILOG语言描述的AMI码的解码的程序,经过调试是正确的。代码简单易懂。(This code is described in VERILOG language AMI code decoding process, after debugging is correct. Code is easy to understand.)
- 2021-04-22 14:48:48下载
- 积分:1
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16点FFT verilog 代码
16点FFT的verilog实现,可以在FPGA上实现,实现硬件加速
- 2022-02-22 07:15:24下载
- 积分:1